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nov 2007 1/79 ST62T55CM-AUTO st62t65cm-auto 8-bit otp/eprom/fastrom mcus with a/d converter, safe reset, auto-reload timer, eeprom and spi 3.0 to 6.0v supply operating range 8 mhz maximum clock frequency -40 to +125c operating temperature range run, wait and stop modes 5 interrupt vectors look-up table capabilit y in program memory data storage in program memory: user selectable size data ram: 128 bytes data eeprom: 128 bytes (none on st62t55c) user programmable options (otp and eprom only) 21 i/o pins, fully programmable as: ? input with pull-up resistor ? input without pull-up resistor ? input with interrupt generation ? open-drain or push-pull output ? analog input 8 i/o lines can sink up to 30ma to drive leds or triacs directly 8-bit timer / counter with 7-bit programmable prescaler 8-bit auto-reload timer with 7-bit programmable prescaler (ar timer) digital watchdog oscillator safe guard low voltage detector for safe reset 8-bit a/d converter with 13 analog inputs 8-bit synchronous peripheral interface (spi) on-chip clock oscillator can be driven by quartz crystal ceramic resonator or rc network user configurable power-on reset one external non-maskable interrupt st626x-emu2 emulation and development system (connects to an ms-dos pc via a parallel port) device summary note: 1. t = one-time programmable; e = eprom/eeprom; p = fastrom ps028 (see end of datasheet for ordering information) cdip28w device 1) otp eprom (bytes) eeprom fastrom (bytes) ST62T55CM-AUTO 3884 - - - st62t65cm-auto 3884 - 128 - st62e65c - 3884 128 - st62p55cm-auto - - - 1836 st62p65cm-auto - - 64 1836 rev. 1
2/79 table of contents 79 document page ST62T55CM-AUTO, st62t65cm-auto . . . . . . . . . . . . . . . . . . . . 1 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.2 program space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3.3 data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.4 stack space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.5 data window register (dwr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.6 data ram/eeprom bank register (drbr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3.7 eeprom description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4.1 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4.2 eprom erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 clocks, reset, interrupts and power saving modes . . . . . . . . . . . . . . . . . . . . . 17 3.1 clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.1 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.2 low frequency auxiliary oscillato r (lfao) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.3 oscillator safe guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.1 reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 3.2.2 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.3 watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.4 lvd reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.5 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.6 mcu initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 digital watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.1 digital watchdog register (dwdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.2 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.1 interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.2 interrupt procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4.3 interrupt option register (ior) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.4.4 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 3.5 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 3.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5.3 exit from wait and stop modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.1 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.1.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.1.2 safe i/o state switching sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3/79 table of contents 79 document page 4.1.3 timer 1 alternate function option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.1.4 ar timer alternate function option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.1.5 spi alternate function option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.2.1 timer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2.2 timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2.3 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.2.4 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 4.3 auto-reload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3.1 ar timer description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3.2 timer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3.3 ar timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.4 a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.4.1 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.5 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.5.1 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.6 spi timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5 software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.1 st6 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.2 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.4 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.5 a/d converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.6 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.7 spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.8 artimer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.2 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.3 otp/eprom version ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.4 important note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 7.5 fastrom version general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.6 fastrom version ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.6.1 transfer of customer code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.6.2 listing generation and verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8 summary of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4/79 ST62T55CM-AUTO st62t65cm-auto 1 general description 1.1 introduction the st62t55c, st62t65c and st62e65c devic - es are low cost members of the st62xx 8-bit hc - mos family of microcontro llers, which is targeted at low to medium complexity applications. all st62xx devices are based on a building block ap - proach: a common core is surrounded by a number of on-chip peripherals. the st62e65c is the erasable eprom version of the st62t65c device, which may be used to em - ulate the st62t55c and st62t65c device, as well as the respective st6255c and st6265c rom devices. otp and eprom devices are functionally identi - cal. the rom based versions offer the same func - tionality selecting as rom options the options de - fined in the programmable option byte of the otp/ eprom versions. otp devices offer all the advantages of user pro - grammability at low cost , which make them the ideal choice in a wide range of applications where frequent code changes, multiple code versions or last minute programm ability are required. these compact low-cost devices feature a timer comprising an 8-bit counter and a 7-bit program - mable prescaler, an 8-bit auto-reload timer, eeprom data capabilit y (except st62t55c), a serial port communication interface, an 8-bit a/d converter with 13 analog inputs and a digital watchdog timer, making them well suited for a wide range of automotive, appliance and industrial applications. figure 1. block diagram j test nmi interrupt program pc stack level 1 stack level 2 stack level 3 stack level 4 stack level 5 stack level 6 power supply oscillator reset data rom user selectable data ram port a port b timer digital 8 bit core test/v pp 8-bit a/d converter pa0..pa7 / ain pb0..pb5 / 30 ma sink v dd v ss oscin oscout reset watchdog memory pb6 / artimin / 30 ma sink port c pc2 / sin / ain pc3 / sout / ain spi (serial peripheral interface) autoreload timer pc4 / sck / ain pb7 / artimout / 30 ma sink 128 bytes 3884 bytes (st62t55c, t65c, data eeprom 128 bytes pc0 / ain pc1 / tim1 / ain (st62t65c/e65c) e65c)
5/79 ST62T55CM-AUTO st62t65cm-auto 1.2 pin descriptions v dd and v ss . power is supplied to the mcu via these two pins. v dd is the power connection and v ss is the ground connection. oscin and oscout. these pins are internally connected to the on-chip o scillator circuit. a quartz crystal, a ceramic resonator or an external clock signal can be connected between these two pins. the oscin pin is the input pin, the oscout pin is the output pin. reset . the active-low reset pin is used to re - start the microcontroller. test/v pp . the test must be held at v ss for nor - mal operation. if test pin is connected to a +12.5v level during the reset phase, the eprom/ otp programming mode is entered. nmi . the nmi pin provides the capability for asyn - chronous interruption, by applying an external non maskable interrupt to the mcu. the nmi input is falling edge sensitive. it is provided with an on-chip pullup resistor (if option has been enabled), and schmitt trigger characteristics. pa0-pa7. these 8 lines are organized as one i/o port (a). each line may be configured under soft - ware control as inputs wit h or without internal pull- up resistors, interrupt generating inputs with pull- up resistors, open-drain or push-pull outputs, ana - log inputs for the a/d converter. pb0-pb5. these 6 lines are organized as one i/o port (b). each line may be configured under soft - ware control as inputs wit h or without internal pull- up resistors, interrupt generating inputs with pull- up resistors, open-drain or push-pull outputs. pb0-pb5 can also sink 30ma for direct led driving. pb6/artimin, pb7/artimout . these pins are ei - ther port b i/o bits or the input and output pins of the ar timer. to be used as timer input function pb6 has to be programmed as input with or with - out pull-up. a dedicated bit in the ar timer mode control register sets pb7 as timer output function. pb6-pb7 can also sink 30ma for direct led driv - ing. pc0-pc4 . these 5 lines are organized as one i/o port (c). each line may be configured under soft - ware control as input with or without internal pull- up resistor, interrupt generating input with pull-up resistor, analog input for the a/d converter, open- drain or push-pull output. pc1 can also be used as timer i/o bit while pc2-pc4 can also be used as respectively data in, data out and clock i/o pins for the on-chip spi to carry the synchronous serial i/o signals. figure 2. st62t55c, t65c, e65c pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 pb0 pb1 v pp /test pb2 pb3 ain / pa0 v dd pb4 pb5 artimin/pb6 pc0/ain pc1/tim1/ain pc2/sin/ain pc3/sout/ain pc4/sck/ain pa7/ain pa6/ain pa5/ain pa4/ain pa3/ain 28 27 26 25 24 23 22 21 artimout/pb7 v ss ain/pa1 ain/pa2 nmi reset oscout oscin
6/79 ST62T55CM-AUTO st62t65cm-auto 1.3 memory map 1.3.1 introduction the mcu operates in three separate memory spaces: program space, data space, and stack space. operation in these three memory spaces is described in the following paragraphs. briefly, program space contains user program code in otp and user vectors; data space con - tains user data in ram and in otp, and stack space accommodates six levels of stack for sub - routine and interrupt service routine nesting. figure 3memory addressing diagram program space program interrupt & reset vectors accumulator data ram bank select window select ram x register y register v register w register data read-only window ram / eeprom banking area 000h 03fh 040h 07fh 080h 081h 082h 083h 084h 0c0h 0ffh 0-63 data space 0000h 0ff0h 0fffh memory memory data read-only memory
7/79 ST62T55CM-AUTO st62t65cm-auto memory map (cont?d) 1.3.2 program space program space comprises the instructions to be executed, the data required for immediate ad - dressing mode instructions, the reserved factory test area and the user vectors. program space is addressed via the 12-bit program counter register (pc register). 1.3.2.1 program memory protection the program memory in otp or eprom devices can be protected against external readout of mem - ory by selecting the readout protection op - tion in the option byte. in the eprom parts, readout protection option can be disactivated only by u.v. erasure that also results into the whole eprom context erasure. note: once the readout protection is activated, it is no longer possible, even for stmicroelectronics, to gain access to the otp contents. returned parts with a protection set can therefore not be ac - cepted. figure 4.st62t55c/t65c/e65c program memory map 0000h reserved * user program memory (otp/eprom) 3872 bytes 0f9fh 0fa0h 0fefh 0ff0h 0ff7h 0ff8h 0ffbh 0ffch 0ffdh 0ffeh 0fffh reserved * reserved interrupt vectors nmi vector user reset vector (*) reserved areas shou ld be filled with 0ffh 0080h 007fh
8/79 ST62T55CM-AUTO st62t65cm-auto memory map (cont?d) 1.3.3 data space data space accommodates all the data necessary for processing the user program. this space com - prises the ram resource, the processor core and peripheral registers, as well as read-only data such as constants and look-up tables in otp/ eprom. 1.3.3.1 data rom all read-only data is physically stored in program memory, which also accommodates the program space. the program memory consequently con - tains the program code to be executed, as well as the constants and look-up tables required by the application. the data space locations in which the different constants and look-up tables are addressed by the processor core may be thought of as a 64-byte window through which it is possible to access the read-only data stored in otp/eprom. 1.3.3.2 data ram/eeprom in st6255cm-auto, st6265cm-auto devices, the data space includes 60 bytes of ram, the accu - mulator (a), the indirect registers (x), (y), the short direct registers (v), (w), the i/o port registers, the peripheral data and control registers, the interrupt option register and the data rom window register (drw register). additional ram and eeprom pages can also be addressed using banks of 64 bytes located be - tween addresses 00h and 3fh. 1.3.4 stack space stack space consists of six 12-bit registers which are used to stack subroutine and interrupt return addresses, as well as the current program counter contents. table 1. additiona l ram/eeprom banks table 2. st6255cm-auto, st6265cm-auto data memory space device ram eeprom st62t55c 1 x 64 bytes - st62t65c/e65c 1 x 64 bytes 2 x 64 bytes ram and eeprom 000h 03fh data rom window area 040h 07fh x register 080h y register 081h v register 082h w register 083h data ram 60 bytes 084h 0bfh port a data register 0c0h port b data register 0c1h port c data register 0c2h reserved 0c3h port a direction register 0c4h port b direction register 0c5h port c direction register 0c6h reserved 0c7h interrupt option register 0c8h* data rom window register 0c9h* reserved 0cah 0cbh port a option register 0cch port b option register 0cdh port c option register 0ceh reserved 0cfh a/d data register 0d0h a/d control register 0d1h timer prescaler register 0d2h timer counter register 0d3h timer status control register 0d4h ar timer mode control register 0d5h ar timer status/control register1 0d6h ar timer status/control register2 0d7h watchdog register 0d8h ar timer reload/capture register 0d9h ar timer compare register 0dah ar timer load register 0dbh oscillator control register 0dch* miscellaneous 0ddh reserved 0deh 0dfh spi data register 0e0h spi divider register 0e1h spi mode register 0e2h reserved 0e3h 0e7h data ram/eeprom register 0e8h* reserved 0e9h eeprom control register 0eah reserved 0ebh 0feh accumulator 0ffh * write only register
9/79 ST62T55CM-AUTO st62t65cm-auto memory map (cont?d) 1.3.5 data window register (dwr) the data read-only memory window is located from address 0040h to address 007fh in data space. it allows direct reading of 64 consecutive bytes locat - ed anywhere in program memory, between ad - dress 0000h and 0fffh (top memory address de - pends on the specific device). all the program memory can therefore be used to store either in - structions or read-only data. indeed, the window can be moved in steps of 64 bytes along the pro - gram memory by writing the appropriate code in the data window register (dwr). the dwr can be addressed like any ram location in the data space, it is however a write-only regis - ter and therefore cannot be accessed using single- bit operations. this register is used to position the 64-byte read-only data window (from address 40h to address 7fh of the data space) in program memory in 64-byte steps. the effective address of the byte to be read as data in program memory is obtained by concatenating the 6 least significant bits of the register address given in the instruction (as least significant bits) and the content of the dwr register (as most significant bits), as illustrat - ed in figure 5 below. for instance, when address - ing location 0040h of the data space, with 0 load - ed in the dwr register, the physical location ad - dressed in program memory is 00h. the dwr reg - ister is not cleared on reset, therefore it must be written to prior to the first access to the data read- only memory window area. data window register (dwr) address: 0c9h ? write only bits 6, 7 = not used. bit 5-0 = dwr5-dwr0: data read-only memory window register bits. these are the data read- only memory window bits that correspond to the upper bits of the data read-only memory space. caution: this register is undefined on reset. nei - ther read nor single bit instructions may be used to address this register. note: care is required when handling the dwr register as it is write only. for this reason, the dwr contents should not be changed while exe - cuting an interrupt service routine, as the service routine cannot save and then restore the register?s previous contents. if it is impossible to avoid writ - ing to the dwr during the interrupt service routine, an image of the register must be saved in a ram location, and each time the program writes to the dwr, it must also write to the image register. the image register must be written first so that, if an in - terrupt occurs between the two instructions, the dwr is not affected. figure 5data read-only memory window memory addressing 7 0 - - dwr5 dwr4 dwr3 dwr2 dwr1 dwr0 data rom window register contents data space address 40h-7fh in instruction program space address 765432 0 543210 543210 read 1 6 7 8 9 10 11 0 1 vr01573c 12 1 0 data space address : : 59h 0 0 0 0 1 00 1 1 1 example: (dwr) dwr=28h 11 000 00 00 1 rom address:a19h 11 13 0 1
10/79 ST62T55CM-AUTO st62t65cm-auto memory map (cont?d) 1.3.6 data ram/eeprom bank register (drbr) address: e8h ? write only bit 7-5 = these bits are not used bit 4 - drbr4 . this bit, when set, selects ram page 2. bit 3-2 - reserved. these bits are not used. bit 1 - drbr1 . this bit, when set, selects eeprom page 1, when available. bit 0 - drbr0 . this bit, when set, selects eeprom page 0, when available. the selection of the bank is made by programming the data ram bank switch register (drbr regis - ter) located at address e8h of the data space ac - cording to table 1. no more than one bank should be set at a time. the drbr register can be addressed like a ram data space at the address e8h; nevertheless it is a write only register that cannot be accessed with single-bit operations. this register is used to select the desired 64-b yte ram/eeprom bank of the data space. the bank number has to be loaded in the drbr register and the instruction has to point to the selected location as if it was in bank 0 (from 00h address to 3fh address). this register is not clea red during the mcu initiali - zation, therefore it must be written before the first access to the data space bank region. refer to the data space description for additional informa - tion. the drbr register is not modified when an interrupt or a subroutine occurs. notes : care is required when handling the drbr register as it is write only. for this reason, it is not allowed to change the drbr contents while executing in - terrupt service routine, as the service routine can - not save and then restore its previous content. if it is impossible to avoid the wr iting of this register in interrupt service routine, an image of this register must be saved in a ram location, and each time the program writes to drbr it must write also to the image register. the image register must be written first, so if an interrupt occurs between the two instructions the drbr is not affected. in drbr register, only 1 bit must be set. other - wise two or more pages are enabled in parallel, producing errors. care must also be taken not to change the e2prom page (when available) when the parallel writing mode is set for the e2prom, as defined in eectl register. table 3data ram bank register set-up 7 0 - - - drbr 4 - - drbr 1 drbr 0 drbr st62t55c st62t65c/e65c 00 none none 01 not available eeprom page 0 02 not available eeprom page 1 08 not available not available 10h ram page 2 ram page 2 other reserved reserved
11/79 ST62T55CM-AUTO st62t65cm-auto memory map (cont?d) 1.3.7 eeprom description eeprom memory is located in 64-byte pages in data space. this memory may be used by the user program for non-volatile data storage. data space from 00h to 3fh is paged as described in table 4 . eeprom locations are accessed di - rectly by addressing these paged sections of data space. the eeprom does not require dedicated instruc - tions for read or write access. once selected via the data ram bank regist er, the active eeprom page is controlled by the eeprom control regis - ter (eectl), which is described below. bit e20ff of the eectl register must be reset prior to any write or read access to the eeprom. if no bank has been selected, or if e2off is set, any ac - cess is meaningless. programming must be enabled by setting the e2ena bit of the eectl register. the e2busy bit of the eectl register is set when the eeprom is performing a programming cycle. any access to the eeprom when e2busy is set is meaningless. provided e2off and e2bu sy are reset, an eep - rom location is read just like any other data loca - tion, also in terms of access time. writing to the eeprom may be carried out in two modes: byte mode (bmo de) and parallel mode (pmode). in bmode, one byte is accessed at a time, while in pmode up to 8 bytes in the same row are programmed simultaneously (with conse - quent speed and power consumption advantages, the latter being particularl y important in battery powered circuits). general notes : data should be written directly to the intended ad - dress in eeprom space. t here is no buffer mem - ory between data ram and the eeprom space. when the eeprom is busy (e2busy = ?1?) eectl cannot be accessed in write mode, it is only possible to read the status of e2busy. this implies that as long as the eeprom is busy, it is not possible to change the status of the eeprom control register. eectl bits 4 and 5 are reserved and must never be set. care is required when dealing with the eectl reg - ister, as some bits are wr ite only. for this reason, the eectl contents must not be altered while ex - ecuting an interrupt service routine. if it is impossible to avoi d writing to this register within an interrupt service routine, an image of the register must be saved in a ram location, and each time the program writes to eectl it must also write to the image register. the image register must be written to first so that, if an interrupt oc - curs between the two inst ructions, the eectl will not be affected. table 4row arrangement for parallel writing of eeprom locations note : the eeprom is disabled as soon as stop instruction is executed in order to achieve the lowest power-consumption. dataspace addresses. banks 0 and 1. byte 0 1 2 3 4 5 6 7 row7 38h-3fh row6 30h-37h row5 28h-2fh row4 20h-27h row3 18h-1fh row2 10h-17h row1 08h-0fh row0 00h-07h up to 8 bytes in each row may be programmed simultaneously in parallel write mode. the number of available 64-byte banks (1 or 2) is device dependent.
12/79 ST62T55CM-AUTO st62t65cm-auto memory map (cont?d) additional notes on parallel mode: if the user wishes to perform parallel program - ming, the first step should be to set the e2par2 bit. from this time on, the eeprom will be ad - dressed in write mode, the row address and the data will be latched and it will be possible to change them only at the end of the programming cycle or by resetting e2par2 without program - ming the eeprom. after the row address is latched, the mcu can only ?see? the selected eeprom row and any attempt to write or read other rows will produce errors. the eeprom should not be read while e2par2 is set. as soon as the e2par2 bit is set, the 8 volatile row latches are cleared. from this moment on, the user can load data in all or in part of the row. setting e2par1 will modify the eeprom regis - ters corresponding to the row latches accessed after e2par2. for example, if the software sets e2par2 and accesses the eeprom by writing to addresses 18h, 1ah and 1bh, and then sets e2par1, these three registers will be modified si - multaneously; the remainin g bytes in the row will be unaffected. note that e2par2 is internally reset at the end of the programming cycle. this implies that the user must set the e2par2 bit between two parallel pro - gramming cycles. note that if the user tries to set e2par1 while e2par2 is not set, there will be no programming cycle and th e e2par1 bit will be un - affected. consequently, the e2par1 bit cannot be set if e2ena is low. the e2par1 bit can be set by the user, only if the e2ena and e2par2 bits are also set. notes : the eeprom page sh all not be changed through the drbr register when the e2par2 bit is set. eeprom control register (eectl) address: eah ? read/write reset status: 00h bit 7 = d7 : unused. bit 6 = e2off : stand-by enable bit. write only. if this bit is set the eeprom is disabled (any access will be meaningless) and the power consumption of the eeprom is reduced to its lowest value. bit 5-4 = d5-d4 : reserved. must be kept reset. bit 3 = e2par1 : parallel start bit. write only. once in parallel mode, as soon as the user software sets the e2par1 bit, parallel writing of the 8 adja - cent registers will start. this bit is internally reset at the end of the programming procedure. note that less than 8 bytes can be written if required, the un - defined bytes being unaffected by the parallel pro - gramming cycle; this is explained in greater detail in the additional notes on parallel mode overleaf. bit 2 = e2par2 : parallel mode en. bit. write only. this bit must be set by the user program in order to perform parallel programming. if e2par2 is set and the parallel start bit (e2par1) is reset, up to 8 adjacent bytes can be written simultane - ously. these 8 adjacent byte s are considered as a row, whose address lines a7, a6, a5, a4, a3 are fixed while a2, a1 and a0 are the changing bits, as illustrated in figure 4 . e2par2 is automatically re - set at the end of any parallel programming proce - dure. it can be reset by the user software before starting the programming procedure, thus leaving the eeprom registers unchanged. bit 1 = e2busy : eeprom busy bit. read on - ly. this bit is automatically set by the eeprom control logic when the eeprom is in program - ming mode. the user program should test it before any eeprom read or write operation; any attempt to access the eeprom while the busy bit is set will be aborted and the writing procedure in progress will be completed. bit 0 = e2ena : eeprom enable bit. write on - ly. this bit enables programming of the eeprom cells. it must be set before any write to the eep - rom register. any attempt to write to the eep - rom when e2ena is low is meaningless and will not trigger a write cycle. 7 0 d7 e2o ff d5 d4 e2pa r1 e2pa r2 e2bu sy e2e na
13/79 ST62T55CM-AUTO st62t65cm-auto 1.4 programming modes 1.4.1 option bytes the two option bytes allo w configuration capabili - ty to the mcus. option byte?s content is automati - cally read, and the selected options enabled, when the chip reset is activated. it can only be accessed during the programming mode. this access is made either automatically (copy from a master device) or by selecting the option byte programming mode of the pro - grammer. the option bytes are located in a non-user map. no address has to be specified. eprom code option byte (lsb) eprom code option byte (msb) d15-d13. reserved. must be cleared. adc synchro . when set, an a/d conversion is started upon wait instruction execution, in order to reduce supply noise. when this bit is low, an a/ d conversion is started as soon as the sta bit of the a/d converter control register is set. d11-d10 . reserved , must be cleared. nmi pull . nmi pull-up . this bit must be set high to configure the nmi pin with a pull-up resistor. when it is low, no pull-up is provided. lvd. lvd reset enable. when this bit is set, safe reset is performed by mcu when the supply voltage is too low. when this bit is cleared, only power-on rese t or external r eset are active. protect . readout protection. this bit allows the protection of the software contents against piracy. when the bit protect is set high, readout of the otp contents is prevented by hardware.. when this bit is low, the user program can be read. extcntl. external stop mode control . . when extcntl is high, stop mode is available with watchdog active by setting nmi pin to one. when extcntl is low, stop mo de is not available with the watchdog active. pb2-3 pull . when set this bit removes pull-up at reset on pb2-pb3 pins. when cleared pb2-pb3 pins have an internal pull-up resistor at reset. pb0-1 pull . when set this bit removes pull-up at reset on pb0-pb1 pins. when cleared pb0-pb1 pins have an internal pull-up resistor at reset. wdact . this bit controls the watchdog activation. when it is high, hardware activation is selected. the software activation is selected when wdact is low. delay . this bit enables the selection of the delay internally generated after the internal reset (exter - nal pin, lvd, or watchdog activated) is released. when delay is low, the delay is 2048 cycles of the oscillator, it is of 32768 cycles when delay is high. oscil . oscillator selection . when this bit is low, the oscillator must be controlled by a quartz crys - tal, a ceramic resonator or an external frequency. when it is high, the oscillator must be controlled by an rc network, with only the resistor having to be externally provided. osgen . oscillator safe guard . this bit must be set high to enable the oscillator safe guard. when this bit is low, the osg is disabled. the option byte is written during programming ei - ther by using the pc menu (pc driven mode) or automatically (stand-alone mode). 7 0 pro - tect extc - ntl pb2-3 pull pb0-1 pull wdact de - lay oscil osgen 15 8 - - - adc synchro - - nmi pull lvd
14/79 ST62T55CM-AUTO st62t65cm-auto programming modes (cont?d) 1.4.2 eprom erasing the eprom of the windowed package of the mcus may be erased by exposure to ultra violet light. the erasure characteristic of the mcus is such that erasure begins when the memory is ex - posed to light with a wave lengths shorter than ap - proximately 4000?. it should be noted that sun - lights and some types of fluorescent lamps have wavelengths in the range 3000-4000?. it is thus recommended that the window of the mcus packages be covered by an opaque label to prevent unintentional erasure problems when test - ing the application in such an environment. the recommended erasure procedure of the mcus eprom is the exposure to short wave ul - traviolet light which have a wave-length 2537a. the integrated dose (i.e. u.v. intensity x exposure time) for erasure should be a minimum of 15w- sec/cm 2 . the erasure time with this dosage is ap - proximately 15 to 20 minutes using an ultraviolet lamp with 12000w/cm 2 power rating. the st62e65c should be placed within 2.5cm (1inch) of the lamp tubes during erasure.
15/79 ST62T55CM-AUTO st62t65cm-auto 2 central processing unit 2.1 introduction the cpu core of st6 devices is independent of the i/o or memory configuration. as such, it may be thought of as an independent central processor communicating with on-chip i/o, memory and pe - ripherals via internal address, data, and control buses. in-core communication is arranged as shown in figure 6 ; the controller being externally linked to both the reset and oscillator circuits, while the core is linked to the dedicated on-chip pe - ripherals via the serial data bus and indirectly, for interrupt purposes, through the control registers. 2.2 cpu registers the st6 family cpu core features six registers and three pairs of flags available to the programmer. these are described in the following paragraphs. accumulator (a) . the accumulator is an 8-bit general purpose register used in all arithmetic cal - culations, logical operations, and data manipula - tions. the accumulator can be addressed in data space as a ram location at address ffh. thus the st6 can manipulate the accumulator just like any other register in data space. indirect registers (x, y). these two indirect reg - isters are used as pointers to memory locations in data space. they are used in the register-indirect addressing mode. these registers can be ad - dressed in the data space as ram locations at ad - dresses 80h (x) and 81h (y). they can also be ac - cessed with the direct, short direct, or bit direct ad - dressing modes. accordingly, the st6 instruction set can use the indirect registers as any other reg - ister of the data space. short direct registers (v, w). these two regis - ters are used to save a byte in short direct ad - dressing mode. they can be addressed in data space as ram locations at addresses 82h (v) and 83h (w). they can also be accessed using the di - rect and bit direct addressing modes. thus, the st6 instruction set can use the short direct regis - ters as any other register of the data space. program counter (pc). the program counter is a 12-bit register which contains the address of the next rom location to be processed by the core. this rom location may be an opcode, an oper - and, or the address of an operand. the 12-bit length allows the direct addressing of 4096 bytes in program space. figure 6. st6 core block diagram program reset opcode flag values 2 controller flags alu a-data b-data address/read line data space interrupts data ram/eeprom data rom/eprom results to data space (write line) rom/eprom dedications accumulator control signals oscin oscout address decoder 256 12 program counter and 6 layer stack 0,01 to 8mhz vr01811
16/79 ST62T55CM-AUTO st62t65cm-auto cpu registers (cont?d) however, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the program bank switch register. the pc value is incremented after reading the ad - dress of the current instruction. to execute relative jumps, the pc and the offset are shifted through the alu, where they are added; the result is then shifted back into the pc. the program counter can be changed in the following ways: - jp (jump) instructionpc=jump address - call instructionpc= call address - relative branch instruction.pc= pc +/- offset - interrupt pc=interrupt vector - reset pc= reset vector - ret & reti instructionspc= pop (stack) - normal instructionpc= pc + 1 flags (c, z) . the st6 cpu includes three pairs of flags (carry and zero), each pair being associated with one of the three normal modes of operation: normal mode, interrupt mode and non maskable interrupt mode. each pair consists of a carry flag and a zero flag. one pair (cn, zn) is used during normal operation, another pair is used dur - ing interrupt mode (ci, zi), and a third pair is used in the non maskable interrupt mode (cnmi, zn - mi). the st6 cpu uses the pair of flags associated with the current mode: as soon as an interrupt (or a non maskable interrupt) is generated, the st6 cpu uses the interrupt flags (resp. the nmi flags) instead of the normal flags. when the reti in - struction is executed, the previously used set of flags is restored. it should be noted that each flag set can only be addressed in its own context (non maskable interrupt, normal interrupt or main rou - tine). the flags are not cleared during context switching and thus retain their status. the carry flag is set when a carry or a borrow oc - curs during arithmetic operations; otherwise it is cleared. the carry flag is also set to the value of the bit tested in a bit test instruction; it also partici - pates in the rotate left instruction. the zero flag is set if the result of the last arithme - tic or logical operation was equal to zero; other - wise it is cleared. switching between the three sets of flags is per - formed automatically when an nmi, an interrupt or a reti instructions occurs. as the nmi mode is automatically selected after the reset of the mcu, the st6 core uses at first the nmi flags. stack. the st6 cpu includes a true lifo hard - ware stack which eliminates the need for a stack pointer. the stack consists of six separate 12-bit ram locations that do not belong to the data space ram area. when a subroutine call (or inter - rupt request) occurs, the contents of each level are shifted into the next higher level, while the content of the pc is shifted into th e first level (the original contents of the sixth stack level are lost). when a subroutine or interrupt return occurs (ret or reti instructions), the first leve l register is shifted back into the pc and the value of each level is popped back into the previous level. since the accumula - tor, in common with all other data space registers, is not stored in this stack, management of these registers should be performed within the subrou - tine. the stack will remain in its ?deepest? position if more than 6 nested calls or interrupts are execut - ed, and consequently the last return address will be lost. it will also remain in its highest position if the stack is empty and a ret or reti is executed. in this case the next instruction will be executed. figure 7. st6 cpu programming mode l short direct addressing mode v register w register program counter six levels stack register cz normal flags interrupt flags nmi flags index register va000423 b7 b7 b7 b7 b7 b0 b0 b0 b0 b0 b0 b11 accumulator y reg. pointer xreg.pointer cz cz
17/79 ST62T55CM-AUTO st62t65cm-auto 3 clocks, reset, interrupts and power saving modes 3.1 clock system the mcu features a main oscillator which can be driven by an external clock, or used in conjunction with an at-cut parallel reso nant crystal or a suita - ble ceramic resonator, or with an external resistor (r net ). in addition, a low frequency auxiliary os - cillator (lfao) can be swit ched in for security rea - sons, to reduce power consumption, or to offer the benefits of a back-up clock system. the oscillator safeguard (osg) option filters spikes from the oscillator lines, provides access to the lfao to provide a ba ckup oscillator in the event of main oscillator failure and also automati - cally limits the internal clock frequency (f int ) as a function of v dd , in order to guarantee correct oper - ation. these functions are illustrated in figure 9 , figure 10 , figure 11 and figure 12 . a programmable divider on f int is also provided in order to adjust the internal clock of the mcu to the best power consumption and performance trade- off. figure 8 illustrates various possible oscillator con - figurations using an external crystal or ceramic res - onator, an external clock input, an external resistor (r net ), or the lowest cost solution using only the lfao. c l1 an c l2 should have a capacitance in the range 12 to 22 pf for an oscillator frequency in the 4-8 mhz range. the internal mcu clock frequency (f int ) is divided by 12 to drive the timer, the a/d converter and the watchdog timer, and by 13 to drive the cpu core, as may be seen in figure 11 . with an 8 mhz oscillator frequency, the fastest ma - chine cycle is therefore 1.625s. a machine cycle is the smallest unit of time needed to execute any operation (for instance, to increment the program counter). an instruction may require two, four, or five machine cycles for execution. 3.1.1 main oscillator the oscillator configuration may be specified by se - lecting the appropriate option. when the crystal/ resonator option is selected , it must be used with a quartz crystal, a ceramic resonator or an external signal provided on the oscin pin. when the rc net - work option is selected, the system clock is gen - erated by an external resistor. the main oscillator can be turned off (when the osg enabled option is selected) by setting the oscoff bit of the adc control register. the low frequency auxiliary o scillator is automatical - ly started. figure 8. oscillator configurations integrated clock crystal/resonator option osg enabled option osc in osc out c l1n c l2 st6xxx crystal/resonator clock crystal/resonator option osc in osc out st6xxx external clock crystal/resonator option nc osc in osc out st6xxx nc osc in osc out r net st6xxx rc network rc network option nc
18/79 ST62T55CM-AUTO st62t65cm-auto clock system (cont?d) turning on the main osc illator is achieved by re - setting the oscoff bit of the a/d converter con - trol register or by resetting the mcu. restarting the main oscillator implie s a delay comprising the oscillator start up delay peri od plus the duration of the software instruction at f lfao clock frequency. 3.1.2 low frequency auxiliary oscillator (lfao) the low frequency auxiliary oscillator has three main purposes. firstly, it can be used to reduce power consumption in non timing critical routines. secondly, it offers a fully integrated system clock, without any external components. lastly, it acts as a safety oscillator in case of main oscillator failure. this oscillator is available when the osg ena - bled option is selected. in this case, it automati - cally starts one of its periods after the first missing edge from the main oscillato r, whatever the reason (main oscillator defective, no clock circuitry provid - ed, main oscillator switched off...). user code, normal interrupts, wait and stop in - structions, are processed as normal, at the re - duced f lfao frequency. the a/d converter accura - cy is decreased, since the internal frequency is be - low 1mhz. at power on, the low fr equency auxiliary oscilla - tor starts faster than the main oscillator. it there - fore feeds the on-chip counter generating the por delay until the main oscillator runs. the low frequency auxilia ry oscillator is auto - matically switched off as soon as the main oscilla - tor starts. adcr address: 0d1h ? read/write bit 7-3, 1-0= adcr7-adcr3, adcr1-adcr0 : adc control register . these bits are reserved for adc control. bit 2 = oscoff . when low, this bit enables main oscillator to run. the main oscillator is switched off when oscoff is high. 3.1.3 oscillator safe guard the oscillator safe guard (osg) affords drastical - ly increased operational integrity in st62xx devic - es. the osg circuit provides three basic func - tions: it filters spikes fr om the oscillator lines which would result in over frequency to the st62 cpu; it gives access to the low frequency auxiliary os - cillator (lfao), used to ensure minimum process - ing in case of main osc illator failure, to offer re - duced power consumption or to provide a fixed fre - quency low cost oscillator; finally, it automatically limits the internal clock frequency as a function of supply voltage, in order to ensure correct opera - tion even if the power supply should drop. the osg is enabled or di sabled by choosing the relevant osg option. it may be viewed as a filter whose cross-over frequency is device dependent. spikes on the oscillator lines result in an effectively increased internal clock frequency. in the absence of an osg circuit, this may lead to an over fre - quency for a given power supply voltage. the osg filters out such spikes (as illustrated in figure 9 ). in all cases, when the osg is active, the maxi - mum internal clock frequency, f int , is limited to f osg , which is supply voltage dependent. this re - lationship is illustrated in figure 12 . when the osg is enabled, the low frequency auxiliary oscillator may be accessed. this oscilla - tor starts operating after the first missing edge of the main oscillator (see figure 10 ). over-frequency, at a given power supply level, is seen by the osg as spikes; it therefore filters out some cycles in order that the internal clock fre - quency of the device is kept within the range the particular device can stand (depending on v dd ), and below f osg : the maximum authorised frequen - cy with osg enabled. note. the osg should be used wherever possible as it provides maximum safety. care must be tak - en, however, as it can increase power consump - tion and reduce the maximum operating frequency to f osg . warning : care has to be taken when using the osg, as the internal frequency is defined between a minimum and a maximum value and is not accu - rate. for precise timing measurements, it is not recom - mended to use the osg and it should not be ena - bled in applications that use the spi or the uart. it should also be noted that power consumption in stop mode is higher when the osg is enabled (around 50a at nominal conditions and room temperature). 7 0 adcr 7 adcr 6 adcr 5 adcr 4 adcr 3 osc off adcr 1 adcr 0
19/79 ST62T55CM-AUTO st62t65cm-auto clock system (cont?d) figure 9. osg filtering principle figure 10. osg emergency oscillator principle (1) vr001932 (3) (2) (4) (1) (2) (3) (4) maximum frequency for the device to work correctly actual quartz crystal frequency at oscin pin noise from oscin resulting internal frequency main vr001933 internal emergency oscillator frequency oscillator
20/79 ST62T55CM-AUTO st62t65cm-auto clock system (cont?d) oscillator control registers address: dch ? write only reset state: 00h bit 7-4. these bits are not used. bit 3. reserved. cleared at reset. must be kept cleared. bit 2. reserved. must be kept low. rs1-rs0. these bits select the division ratio of the oscillator divider in or der to generate the inter - nal frequency. the following selctions are availa - ble: note : care is required when handling the oscr register as some bits are write only. for this rea - son, it is not allowed to change the oscr contents while executing interrupt service routine, as the service routine cannot save and then restore its previous content. if it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a ram location, and each time the program writes to oscr it must write also to the image register. the image register must be writ ten first, so if an inter - rupt occurs between the two instructions the oscr is not affected. 7 0 - - - - oscr 3 - rs1 rs0 rs1 rs0 division ratio 0 0 1 1 0 1 0 1 1 2 4 4
21/79 ST62T55CM-AUTO st62t65cm-auto clock system (cont?d) figure 11. clock circuit block diagram figure 12. maximum operating frequency (f max ) versus supply voltage (v dd ) notes : 1. in this area, operation is guaranteed at the quartz crystal frequency. 2. when the osg is disabled, operation in this area is guaranteed at the crystal frequency. when the osg is enabled, operation in this area is guar - anteed at a frequency of at least f osg min. 3. when the osg is disabled, operation in this area is guaranteed at the quartz crystal frequency. when the osg is enabled, access to this area is prevented. the internal frequency is kept a f osg. 4. when the osg is disabled, operation in this area is not guaranteed when the osg is enabled, access to this area is prevented. the internal frequency is kept at f osg. main oscillator osg lfao m u x core : 13 : 12 : 1 timer 1 watchdog por f int main oscillator off oscillator divider rs0,rs1 1 2.5 3.644.555.56 8 7 6 5 4 3 2 maximum frequency (mhz) supply voltage (v dd ) functionality is not 3 4 3 2 1 f osg f osg min (at 85c) guaranteed in this area vr01807j f osg min (at 125c)
22/79 ST62T55CM-AUTO st62t65cm-auto 3.2 resets the mcu can be reset in four ways: ? by the external reset input being pulled low; ? by power-on reset; ? by the digital watchdog peripheral timing out. ? by low voltage detection (lvd) 3.2.1 reset input the reset pin may be connected to a device of the application board in order to reset the mcu if required. the reset pin may be pulled low in run, wait or stop mode. this input can be used to reset the mcu internal state and ensure a correct start-up procedure. the pin is active low and features a schmitt trigger input. the internal reset signal is generated by adding a delay to the external signal. therefore even short pulses on the reset pin are acceptable, provided v dd has completed its rising phase and that the oscillator is running correctly (normal run or wait modes). the mcu is kept in the reset state as long as the reset pin is held low. if reset activation occurs in the run or wait modes, processing of the user program is stopped (run mode only), the inputs and outputs are con - figured as inputs with pull-up resistors and the main oscillator is restart ed. when the level on the reset pin then goes hi gh, the initialization se - quence is executed following expiry of the internal delay period. if reset pin activation occurs in the stop mode, the oscillator starts up a nd all inputs and outputs are configured as inputs with pull-up resistors. when the level of the reset pin then goes high, the initialization sequen ce is executed following expiry of the internal delay period. 3.2.2 power-on reset the function of the por circuit consists in waking up the mcu by detecting around 2v a dynamic (rising edge) variation of the vdd supply. at the beginning of this sequence, the mcu is configured in the reset state: all i/o ports are configured as inputs with pull-up resistors and no instruction is executed. when the power supply voltage rises to a sufficient level, the osc illator starts to operate, whereupon an internal delay is initiated, in order to allow the oscillator to fu lly stabilize before execut - ing the first instruction. the initialization sequence is executed immediately following the internal de - lay. to ensure correct start-up, the user should take care that the vdd supply is stabilized at a suffi - cient level for the chosen frequency (see recom - mended operation) before the reset signal is re - leased. in addition, supply rising must start from 0v. as a consequence, the por does not allow to su - pervise static, slowly rising, or falling, or noisy (presenting oscillation) vdd supplies. an external rc network connected to the reset pin, or the lvd reset can be used instead to get the best performances. figure 13. reset and interrupt processing int latch cleared nmi mask set reset ( if present ) select nmi mode flags is reset still present? yes put ffeh on address bus from reset locations ffe/fff no fetch instruction load pc va000427
23/79 ST62T55CM-AUTO st62t65cm-auto resets (cont?d) 3.2.3 watchdog reset the mcu provides a watchdog timer function in order to ensure graceful recovery from software upsets. if the watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be acti vated. this, amongst oth - er things, resets the watchdog counter. the mcu restarts just as though the reset had been generated by the reset pin, including the built-in stabilisation delay period. 3.2.4 lvd reset the on-chip low voltage detector, selectable as user option, features static reset when supply voltage is below a reference value. thanks to this feature, external reset circuit can be removed while keeping the applic ation safety. this safe reset is effective as we ll in power-on phase as in power supply drop with different reference val - ues, allowing hysteresis e ffect. reference value in case of voltage drop has been set lower than the reference value for power-on in order to avoid any parasitic reset when mcu start's running and sinking current on the supply. as long as the supply voltage is below the refer - ence value, there is a internal and static reset command. the mcu can start only when the sup - ply voltage rises over the reference value. there - fore, only two operating mode exist for the mcu: reset active below the voltage reference, and running mode over the voltage reference as shown on the figure 14 , that represents a power- up, power-down sequence. note : when the reset state is controlled by one of the internal reset sources (low voltage de - tector, watchdog, power on reset), the reset pin is tied to low logic level. figure 14. lvd reset on power-on and power-down (brown-out) 3.2.5 application notes no external resistor is required between v dd and the reset pin, thanks to the built-in pull-up device. direct external connection of the pin reset to v dd must be avoided in order to ensure safe be - haviour of the internal reset sources (and.wired structure). reset reset vr02106a time v up v dn v dd
24/79 ST62T55CM-AUTO st62t65cm-auto resets (cont?d) 3.2.6 mcu initialization sequence when a reset occurs the stack is reset, the pc is loaded with the address of the reset vector (locat - ed in program rom starting at address 0ffeh). a jump to the beginning of the user program must be coded at this address. following a reset, the in - terrupt flag is automatically set, so that the cpu is in non maskable interrupt mode; this prevents the initialisation routine from being interrupted. the in - itialisation routine should therefore be terminated by a reti instruction, in order to revert to normal mode and enable interrupts. if no pending interrupt is present at the end of the initialisation routine, the mcu will continue by proc essing the instruction immediately following the re ti instruction. if, how - ever, a pending interrupt is present, it will be serv - iced. figure 15. reset and interrupt processing figure 16. reset block diagram reset reset vector jp jp:2 bytes/4 cycles reti reti: 1 byte/2 cycles initialization routine va00181 v dd reset r pu r esd 1) power watchdog reset ck counter reset st6 internal reset f osc reset on reset lvd reset vr02107a and. wired 1) resistive esd protection. value not guaranteed.
25/79 ST62T55CM-AUTO st62t65cm-auto resets (cont?d) table 5register reset status register address(es) status comment oscillator control register eeprom control register port data registers port direction register port option register interrupt option register timer status/control ar timer mode control register ar timer status/control 0 register ar timer status/control 1 register ar timer compare register ar timer load register miscellaneous register spi registers spi div register spi mod register spi dsr register 0dch 0eah 0c0h to 0c2h 0c4h to 0c6h 0cch to 0ceh 0c8h 0d4h 0d5h 0d6h 0d7h 0dah 0dbh 0ddh 0e0h to 0e2h 0e1h 0e2h 0e0h 00h 00h 00h 00h 00h 00h 00h 00h 02h 00h 00h 00h 00h 00h 00h 00h undefined eeprom disabled (if available) i/o are input with pull-up i/o are input with pull-up i/o are input with pull-up interrupt disabled timer disabled ar timer stopped spi output not connected to pc3 spi disabled spi disabled spi disabled spi disabled x, y, v, w, register accumulator data ram data ram eeprom page register data rom window register eeprom a/d result register ar timer load register ar timer reload/capture register 080h to 083h 0ffh 084h to 0bfh 0e8h 0c9h 00h to 03fh 0d0h 0dbh 0d9h undefined as written if programmed timer counter register timer prescaler register watchdog counter register a/d control register 0d3h 0d2h 0d8h 0d1h ffh 7fh feh 40h max count loaded a/d in standby
26/79 ST62T55CM-AUTO st62t65cm-auto 3.3 digital watchdog the digital watchdog co nsists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets. the watchdog circuit generates a reset when the downcounter reaches zero. user software can prevent this reset by reloading the counter, and should therefore be written so that the counter is regularly reloaded while the user program runs correctly. in the event of a software mishap (usual - ly caused by externally generated interference), the user program will no lo nger behave in its usual fashion and the ti mer register will thus not be re - loaded periodically. cons equently the timer will decrement down to 00h and reset the mcu. in or - der to maximise the effectiveness of the watchdog function, user software mu st be written with this concept in mind. watchdog behaviour is governed by two options, known as ?watchdog activation? (i.e. hardware or software) and ?external stop mode control? (see table 6 ). in the software option, the watchdog is disa - bled until bit c of the dwdr register has been set. when the watchdog is disabled, low power stop mode is available. once activated, the watchdog cannot be disabled, except by resetting the mcu. in the hardware option, the watchdog is per - manently enabled. since the oscillator will run con - tinuously, low power mode is not available. the stop instruction is interp reted as a wait instruc - tion, and the watchdog continues to countdown. however, when the external stop mode control option has been selected low power consumption may be achieved in stop mode. execution of the stop instruction is then gov - erned by a secondary function associated with the nmi pin. if a stop instruction is encountered when the nmi pin is low, it is interpreted as wait, as described above. if, however, the stop in - struction is encountered when the nmi pin is high, the watchdog counter is frozen and the cpu en - ters stop mode. when the mcu exits stop mode (i.e. when an in - terrupt is generated), the watchdog resumes its activity. table 6. recommended option choices functions required recommended options stop mode & watchdog ?external stop mode? & ?hardware watchdog? stop mode ?software watchdog? watchdog ?hardware watchdog?
27/79 ST62T55CM-AUTO st62t65cm-auto digital watchdog (cont?d) the watchdog is associated with a data space register (digital watchd og register, dwdr, loca - tion 0d8h) which is described in greater detail in section 3.3.1 digital watchdog register (dwdr) . this register is set to 0feh on reset: bit c is cleared to ?0?, which disables the watchdog; the timer downcounter bits, t0 to t5, and the sr bit are all set to ?1?, thus selecting the longest watch - dog timer period. this time period can be set to the user?s requirements by setting the appropriate val - ue for bits t0 to t5 in the dwdr register. the sr bit must be set to ?1?, since it is this bit which gen - erates the reset signal when it changes to ?0?; clearing this bit would generate an immediate re - set. it should be noted that the order of the bits in the dwdr register is invert ed with respect to the as - sociated bits in the down counter: bit 7 of the dwdr register corresponds, in fact, to t0 and bit 2 to t5. the user should bear in mind the fact that these bits are inverted and shifted with respect to the physical counter bits wh en writing to this regis - ter. the relationship between the dwdr register bits and the physical implementation of the watch - dog timer downcounter is illustrated in figure 17 . only the 6 most significant bits may be used to de - fine the time period, since it is bit 6 which triggers the reset when it changes to ?0?. this offers the user a choice of 64 timed periods ranging from 3,072 to 196,608 clock c ycles (with an oscillator frequency of 8 mhz, this is equivalent to timer peri - ods ranging from 384 s to 24.576 ms). figure 17. watchdog counter control watchdog control register d0 d1 d3 d4 d5 d6 d7 watchdog counter c sr t5 t4 t3 t2 t1 d2 t0 osc 12 reset vr02068a 2 8
28/79 ST62T55CM-AUTO st62t65cm-auto digital watchdog (cont?d) 3.3.1 digital watchdog register (dwdr) address: 0d8h ? read/write reset status: 1111 1110 b bit 0 = c : watchdog control bit if the hardware option is selected, this bit is forced high and the user cannot change it (the watchdog is always active). when the software option is se - lected, the watchdog function is activated by set - ting bit c to 1, and cannot then be disabled (save by resetting the mcu). when c is kept low the counter can be used as a 7-bit timer. this bit is cleared to ?0? on reset. bit 1 = sr : software reset bit this bit triggers a reset when cleared. when c = ?0? (watchdog disabled) it is the msb of the 7-bit timer. this bit is set to ?1? on reset. bits 2-7 = t5-t0 : downcounter bits it should be noted that the register bits are re - versed and shifted with respect to the physical counter: bit-7 (t0) is the lsb of the watchdog downcounter and bit-2 (t5) is the msb. these bits are set to ?1? on reset. 3.3.2 application notes the watchdog plays an important supporting role in the high noise immunity of st62xx devices, and should be used wherever possible. watchdog re - lated options should be selected on the basis of a trade-off between application security and stop mode availability. when stop mode is not required, hardware acti - vation without external stop mode con - trol should be preferred, as it provides maxi - mum security, especially during power-on. when stop mode is required, hardware activa - tion and external stop mode control should be chosen. nmi should be high by default, to allow stop mode to be entered when the mcu is idle. the nmi pin can be connected to an i/o line (see figure 18 ) to allow its state to be controlled by soft - ware. the i/o line can then be used to keep nmi low while watchdog protection is required, or to avoid noise or key bounce. when no more processing is required, the i/o line is released and the device placed in stop mode for lowest power consumption. when software activation is selected and the watchdog is not activated, the downcounter may be used as a simple 7-bit timer (remember that the bits are in reverse order). the software activation option should be chosen only when the watchdog counter is to be used as a timer. to ensure the watchdog has not been un - expectedly activated, the following instructions should be executed within the first 27 instructions: jrr 0, wd, #+3 ldi wd, 0fdh 7 0 t0 t1 t2 t3 t4 t5 sr c
29/79 ST62T55CM-AUTO st62t65cm-auto digital watchdog (cont?d) these instructions test the c bit and reset the mcu (i.e. disable the watchdog) if the bit is set (i.e. if the watchdog is active), thus disabling the watchdog. in all modes, a minimum of 28 instructions are ex - ecuted after activation, before the watchdog can generate a reset. consequently, user software should load the watchdog counter within the first 27 instructions following watchdog activation (software mode), or within the first 27 instructions executed following a reset (hardware activation). it should be noted that when the gen bit is low (in - terrupts disabled), the nmi interrupt is active but cannot cause a wake up from stop/wait modes. figure 18. a typical circuit making use of the exernal stop mode control feature figure 19. digital watchdog block diagram nmi switch i/o vr02002 rsff 8 data bus va00010 -2 -12 oscillator reset write reset db0 r s q db1.7 set load 7 8 -2 set clock
30/79 ST62T55CM-AUTO st62t65cm-auto 3.4 interrupts the cpu can manage four maskable interrupt sources, in addition to a non maskable interrupt source (top priority interrupt). each source is asso - ciated with a specific interrupt vector which con - tains a jump instruction to the associated interrupt service routine. these vectors are located in pro - gram space (see table 7 ). when an interrupt source generates an interrupt request, and interrupt processing is enabled, the pc register is loaded with the address of the inter - rupt vector (i.e. of the jump instruction), which then causes a jump to the relevant interrupt serv - ice routine, thus se rvicing the interrupt. interrupt sources are linked to events either on ex - ternal pins, or on chip peripherals. several events can be ored on the same interrupt source, and relevant flags are available to determine which event triggered the interrupt. the non maskable interrupt request has the high - est priority and can interrupt any interrupt routine at any time; the other four interrupts cannot inter - rupt each other. if more than one interrupt request is pending, these are processed by the processor core according to their prio rity level: source #1 has the higher priority while source #4 the lower. the priority of each interrupt source is fixed. table 7. interrupt vector map 3.4.1 interrupt request all interrupt sources but the non maskable inter - rupt source can be disabled by setting accordingly the gen bit of the interrupt option register (ior). this gen bit also defines if an interrupt source, in - cluding the non maskable interrupt source, can re - start the mcu from stop/wait modes. interrupt request from the non maskable interrupt source #0 is latched by a flip flop which is automat - ically reset by the core at the beginning of the non- maskable interrupt service routine. interrupt request from source #1 can be config - ured either as edge or level sensitive by setting ac - cordingly the les bit of the interrupt option regis - ter (ior). interrupt request from source #2 are always edge sensitive. the edge polarity can be configured by setting accordingly the esb bit of the interrupt op - tion register (ior). interrupt request from sources #3 & #4 are level sensitive. in edge sensitive mode, a latch is set when a edge occurs on the interrupt source line and is cleared when the associated interrupt routine is started. so, the occurrence of an interrupt can be stored, until completion of the running interrupt routine be - fore being processed. if several interrupt requests occurs before completion of the running interrupt routine, only the first request is stored. storage of interrupt requests is not available in lev - el sensitive mode. to be taken into account, the low level must be present on the interrupt pin when the mcu samples the line after instruction execu - tion. at the end of every instruction, the mcu tests the interrupt lines: if there is an interrupt request the next instruction is not executed and the appropri - ate interrupt service routine is executed instead. table 8. interrupt option register description interrupt source priority vector address interrupt source #0 1 (ffch-ffdh) interrupt source #1 2 (ff6h-ff7h) interrupt source #2 3 (ff4h-ff5h) interrupt source #3 4 (ff2h-ff3h) interrupt source #4 5 (ff0h-ff1h) gen set enable all interrupts cleared disable all interrupts esb set rising edge mode on inter - rupt source #2 cleared falling edge mode on inter - rupt source #2 les set level-sensitive mode on in - terrupt source #1 cleared falling edge mode on inter - rupt source #1 others not used
31/79 ST62T55CM-AUTO st62t65cm-auto interrupts (cont?d) 3.4.2 interrupt procedure the interrupt procedure is very similar to a call pro - cedure, indeed the user can consider the interrupt as an asynchronous call procedure. as this is an asynchronous event, the user cannot know the context and the time at which it occurred. as a re - sult, the user should save all data space registers which may be used within the interrupt routines. there are separate sets of processor flags for nor - mal, interrupt and non-maskable interrupt modes, which are automatically switched and so do not need to be saved. the following list summariz es the interrupt proce - dure: mcu ? the interrupt is detected. ? the c and z flags are replaced by the interrupt flags (or by the nmi flags). ? the pc contents are stored in the first level of the stack. ? the normal interrupt lines are inhibited (nmi still active). ? the first internal latch is cleared. ? the associated interrupt vector is loaded in the pc. warning: in some circumstances, when a maskable interrupt occurs while the st6 core is in normal mode and especia lly during the execu - tion of an "ldi ior, 00h" instruction (disabling all maskable interrupts): if the interrupt arrives during the first 3 cycles of the "ldi" instruction (which is a 4-cycle instruction) the co re will switch to interrupt mode but the flags cn and zn will not switch to the interrupt pair ci and zi. user ? user selected registers are saved within the in - terrupt service routine (normally on a software stack). ? the source of the interr upt is found by polling the interrupt flags (if more than one source is associ - ated with the same vector). ? the interrupt is serviced. ? return from interrupt (reti) mcu ? automatically the mcu switches back to the nor - mal flag set (or the interrupt flag set) and pops the previous pc value from the stack. the interrupt routine usually begins by the identify - ing the device which generated the interrupt re - quest (by polling). the user should save the regis - ters which are used within the interrupt routine in a software stack. after the reti instruction is exe - cuted, the mcu returns to the main routine. figure 20. interrupt processing flow chart instruction fetch instruction execute instruction was the instruction a reti ? ? clear interrupt mask select program flags "pop" the stacked pc ? check if there is an interrupt request and interrupt mask select internal mode flag push the pc into the stack load pc from interrupt vector (ffc/ffd) set interrupt mask no no yes is the core already in normal mode? va000014 yes no yes
32/79 ST62T55CM-AUTO st62t65cm-auto interrupts (cont?d) 3.4.3 interrupt option register (ior) the interrupt option register (ior) is used to en - able/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. this register is write-only and cannot be accessed by single-bit operations. address: 0c8h ? write only reset status: 00h bit 7, bits 3-0 = unused . bit 6 = les : level/edge selection bit . when this bit is set to one, the interrupt source #1 is level sensitive. when cleared to zero the edge sensitive mode for interrupt request is selected. bit 5 = esb : edge selection bit . the bit esb selects the polarity of the interrupt source #2. bit 4 = gen : global enable interrupt . when this bit is set to one, all interrupts are enabled. when this bit is cleared to zero all the interrupts (excluding nmi) are disabled. when the gen bit is low, the nmi interrupt is ac - tive but cannot cause a wake up from stop/wait modes. this register is cleared on reset. 3.4.4 interrupt sources interrupt sources available on these mcus are summarized in the table 9 with associated mask bit to enable/disable the interrupt request. table 9interrupt requests and mask bits 7 0 - les esb gen - - - - peripheral register address register mask bit masked interrupt source interrupt vector general ior c8h gen all interrupts, excluding nm i timer tscr1 d4h eti tmz: timer overflow vector 4 a/d converter adcr d1h eai eoc: end of conversion vector 4 ar timer armc d5h ovie cpie eie ovf: ar timer overflow cpf: successful compare ef: active edge on artimin vector 3 spi spimod e2h spie sprun: end of transmission vector 2 port pan orpa-drpa c0h-c4h orpan-drpan pan pin vector 1 port pbn orpb-drpb c1h-c5h orpbn-drpbn pbn pin vector 1 port pcn orpc-drpc c2h-c6h orpcn-drpcn pcn pin vector 2
33/79 ST62T55CM-AUTO st62t65cm-auto interrupts (cont?d) figure 21 interrupt block diagram start 1 i q clk clr ff 1 0 mux ior reg. c8h, bit 6 ior reg. c8h, bit 5 ff clr clk q i 2 start timer1 cpie cpf tmz eti int #4 (ff0,1) int #3 (ff2,3) int #2 (ff4,5) int #1 (ff6,7) restart from stop/wait ar timer ef eie ovf ovie va0426k pbe bits bits port b port a pbe pbe dd v single bit enable from register port a,b,c port c spint bit start 0 i q clk clr ff bit gen (ior register) nmi (ffc,d) nmi v dd adc eoc eai spie bit spidiv register spimod register
34/79 ST62T55CM-AUTO st62t65cm-auto 3.5 power saving modes the wait and stop modes have been imple - mented in the st62xx fam ily of mcus in order to reduce the product?s electrical consumption during idle periods. these two power saving modes are described in the following paragraphs. 3.5.1 wait mode the mcu goes into wait mode as soon as the wait instruction is executed. the microcontroller can be considered as being in a ?software frozen? state where the core stops processing the pro - gram instructions, the ram contents and peripher - al registers are preserved as long as the power supply voltage is higher than the ram retention voltage. in this mode the peripherals are still ac - tive. wait mode can be used when the user wants to reduce the mcu power consumption during idle periods, while not losing track of time or the capa - bility of monitoring extern al events. the active os - cillator is not stopped in order to provide a clock signal to the peripherals. timer counting may be enabled as well as the timer interrupt, before en - tering the wait mode: this allows the wait mode to be exited when a timer interrupt occurs. the same applies to other peripherals which use the clock signal. if the wait mode is exited due to a reset (either by activating the external pin or generated by the watchdog), the mcu enters a normal reset proce - dure. if an interrupt is generated during wait mode, the mcu?s behaviour depends on the state of the processor core prior to the wait instruction, but also on the kind of interrupt request which is generated. this is described in the following para - graphs. the processor core does not generate a delay following the occurrence of the interrupt, be - cause the oscillator clock is still available and no stabilisation period is necessary. 3.5.2 stop mode if the watchdog is disabled, stop mode is availa - ble. when in stop mode, the mcu is placed in the lowest power consumption mode. in this oper - ating mode, the microcontroller can be considered as being ?frozen?, no instruction is executed, the oscillator is stopped, th e ram contents and pe - ripheral registers are preserved as long as the power supply voltage is higher than the ram re - tention voltage, and the st62xx core waits for the occurrence of an external interrupt request or a reset to exit the stop state. if the stop state is exited due to a reset (by acti - vating the external pin) the mcu will enter a nor - mal reset procedure. behaviour in response to in - terrupts depends on the state of the processor core prior to issuing th e stop instruction, and also on the kind of interrupt request that is gener - ated. this case will be described in the following para - graphs. the processor core generates a delay af - ter occurrence of the interrupt request, in order to wait for complete stabilisat ion of the oscillator, be - fore executing the first instruction.
35/79 ST62T55CM-AUTO st62t65cm-auto power saving mode (cont?d) 3.5.3 exit from wait and stop modes the following paragraphs describe how the mcu exits from wait and stop modes, when an inter - rupt occurs (not a reset). it should be noted that the restart sequence depends on the original state of the mcu (normal, interrupt or non-maskable in - terrupt mode) prior to entering wait or stop mode, as well as on the interrupt type. interrupts do not affect the oscillator selection. 3.5.3.1 normal mode if the mcu was in the main routine when the wait or stop instruction was executed, exit from stop or wait mode will occur as soon as an interrupt oc - curs; the related interrupt routine is executed and, on completion, the instru ction which follows the stop or wait instruction is then executed, pro - viding no other interrupts are pending. 3.5.3.2 non maskable interrupt mode if the stop or wait instruction has been execut - ed during execution of the non-maskable interrupt routine, the mcu exits from the stop or wait mode as soon as an interrupt occurs: the instruction which follows the stop or wait instruction is ex - ecuted, and the mcu remains in non-maskable in - terrupt mode, even if another interrupt has been generated. 3.5.3.3 normal interrupt mode if the mcu was in interrupt mode before the stop or wait instruction was executed, it exits from stop or wait mode as soon as an interrupt oc - curs. nevertheless, two cases must be consid - ered: ? if the interrupt is a normal one, the interrupt rou - tine in which the wait or stop mode was en - tered will be completed, starting with the execution of the instru ction which follows the stop or the wait instruction, and the mcu is still in the interrupt mode. at the end of this rou - tine pending inte rrupts will be serviced in accord - ance with their priority. ? in the event of a non-maskable interrupt, the non-maskable interrupt service routine is proc - essed first, then the routine in which the wait or stop mode was entered will be completed by executing the instruction following the stop or wait instruction. the mcu remains in normal interrupt mode. notes: to achieve the lowest power consumption during run or wait modes, the user program must take care of: ? configuring unused i/os as inputs without pull-up (these should be externally tied to well defined logic levels); ? placing all peripherals in their power down modes before entering stop mode; when the hardware activated watchdog is select - ed, or when the software watchdog is enabled, the stop instruction is disabled and a wait instruc - tion will be executed in its place. if all interrupt sources are disabled (gen low), the mcu can only be restarted by a reset. although setting gen low does not mask the nmi as an in - terrupt, it will stop it g enerating a wake-up signal. the wait and stop instructions are not execut - ed if an enabled interrupt request is pending.
36/79 ST62T55CM-AUTO st62t65cm-auto 4 on-chip peripherals 4.1 i/o ports the mcu features input/output lines which may be individually programmed as any of the following input or output configurations: ? input without pull-up or interrupt ? input with pull-up and interrupt ? input with pull-up, but without interrupt ? analog input ? push-pull output ? open drain output the lines are organised as bytewise ports. each port is associated with 3 registers in data space. each bit of these registers is associated with a particular line (for instance, bits 0 of port a data, direction and option registers are associat - ed with the pa0 line of port a). the data registers (drx), are used to read the voltage level values of the lines which have been configured as inputs, or to write the logic value of the signal to be output on the lines configured as outputs. the port data registers can be read to get the effective logic levels of the pins, but they can be also written by user software, in conjunction with the related option registers, to select the dif - ferent input mode options. single-bit operations on i/o registers are possible but care is necessary because reading in input mode is done from i/o pins while writing will direct - ly affect the port data register causing an unde - sired change of the input configuration. the data direction registers (ddrx) allow the data direction (input or output) of each pin to be set. the option registers (orx) are used to select the different port options available both in input and in output mode. all i/o registers can be read or written to just as any other ram location in data space, so no extra ram cells are needed for port data storage and manipulation. during mcu in itialization, all i/o reg - isters are cleared and the input mode with pull-ups and no interrupt generation is selected for all the pins, thus avoiding pin conflicts. figure 22. i/o port block diagram v dd reset s in controls s out shift register data data direction register register option register input/output to interrupt v dd to adc va00413
37/79 ST62T55CM-AUTO st62t65cm-auto i/o ports (cont?d) 4.1.1 operating modes each pin may be individually programmed as input or output with various configurations. this is achieved by writi ng the relevant bit in the data (dr), data direction (ddr) and option reg - isters (or). table 10 illustrates the various port configurations which can be selected by user soft - ware. 4.1.1.1 input options pull-up, high impedance op tion. all input lines can be individually programmed with or without an internal pull-up by programming the or and dr registers accordingly. if the pull-up option is not selected, the input pin will be in the high-imped - ance state. 4.1.1.2 interrupt options all input lines can be individually connected by software to the interrupt system by programming the or and dr registers accordingly. the inter - rupt trigger modes (fallin g edge, rising edge and low level) can be config ured by software as de - scribed in the interrupt chapter for each port. 4.1.1.3 analog input options some pins can be configured as analog inputs by programming the or and dr registers according - ly. these analog inputs are connected to the on- chip 8-bit analog to digital converter. only one pin should be programmed as an analog input at any time, since by selecting more than one input simultaneously their pins will be effectively short - ed. table 10. i/o port option selection note: x = don?t care ddr or dr mode option 0 0 0 input with pull-up, no interrupt 0 0 1 input no pull-up, no interrupt 0 1 0 input with pull-up and with interrupt 0 1 1 input analog input (when available) 1 0 x output open-drain output (20ma sink when available) 1 1 x output push-pull output (20ma sink when available)
38/79 ST62T55CM-AUTO st62t65cm-auto i/o ports (cont?d) 4.1.2 safe i/o state switching sequence switching the i/o ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. the recom - mended safe transiti ons are illustrated in figure 23 . all other transitions are potentially risky and should be avoided when changing the i/o operat - ing mode, as it is most likely that undesirable side- effects will be experienced, such as spurious inter - rupt generation or two pins shorted together by the analog multiplexer. single bit instructions (set, res, inc and dec) should be used with great caution on ports data registers, since these instructions make an implicit read and write back of the entire register. in port input mode, however, the data register reads from the input pins directly, and not from the data regis - ter latches. since data register information in input mode is used to set the characteristics of the input pin (interrupt, pull-up, analog input), these may be unintentionally reprogrammed depending on the state of the input pins. as a general rule, it is better to limit the use of single bit instructions on data registers to when the whole (8-bit) port is in output mode. in the case of inputs or of mixed inputs and outputs, it is advisable to keep a copy of the data register in ram. single bit instructions may then be used on the ram copy, after which the whole copy register can be written to the port data regis - ter: set bit, datacopy ld a, datacopy ld dra, a warning: care must also be taken to not use in - structions that act on a whole port register (inc, dec, or read operations) when all 8 bits are not available on the device. unavailable bits must be masked by software (and instruction). the wait and stop instructions allow the st62xx to be used in situations where low power consumption is needed. the lowest power con - sumption is achieved by configuring i/os in input mode with well-defined logic levels. the user must take care not to switch outputs with heavy loads during the conversion of one of the analog inputs in order to avoid any disturbance to the conversion. figure 23. diagram showing safe i/o state transitions note *. xxx = ddr, or, dr bits respectively interrupt pull-up output open drain output push-pull input pull-up (reset state) input analog output open drain output push-pull input 010* 000 100 110 011 001 101 111
39/79 ST62T55CM-AUTO st62t65cm-auto i/o ports (cont?d) table 11i/o port option selections note 1 . provided the correct configuration has been selected. mode available on (1) schematic input pa0-pa7 pb0-pb5, pb6-pb7 pc0-pc4 input with pull up pa0-pa7 pb0-pb5, pb6-pb7 pc0-pc4 input with pull up with interrupt pa0-pa7 pb0-pb5, pb6-pb7 pc0-pc4 analog input pa0-pa7 pc0-pc4 open drain output 5ma open drain output 30ma pa0-pa7 pc0-pc4 pb0-pb5, pb6-pb7 push-pull output 5ma push-pull output 30ma pa0-pa7 pc0-pc4 pb0-pb5, pb6-pb7 data in interrupt data in interrupt data in interrupt data out adc data out
40/79 ST62T55CM-AUTO st62t65cm-auto i/o ports (cont?d) 4.1.3 timer 1 alternate function option when bit tout of register tscr1 is low, pin pc1/ timer 1 is configured through the port registers as any standard pin of port b. it is in addition connect - ed to the timer 1 input for gated and event coun - ter modes. when bit tout of register tscr1 is high, pin pc1/timer 1 is forced as timer 1 output, independently of the port registers configuration. 4.1.4 ar timer alte rnate function option when bit pwmoe of register armc is low, pin ar - timout/pb7 is configured as any standard pin of port b through the port registers. when pwmoe is high, artimout/pb7 is the pwm output, independ - ently of the port registers configuration. artimin/pb6 is connected to the ar timer input. it is configured through the port registers as any standard pin of port b. to use artimin/pb6 as ar timer input, it must be configured as input through ddrb. 4.1.5 spi alternate function option pc2/pc4 are used as standard i/o as long as bit spclk of the spi mode re gister is kept low. when pc2/sin is configured as input, it is automat - ically connected to the spi shift register input, in - dependent of the state at spclk. pc3/sout is configured as spi push-pull output by setting bit 0 of the miscellaneous register (ad - dress ddh), regardless of the state of port c reg - isters. pc4/sck is configured as push-pull output clock (master mode) by programming it as push- pull output through ddrc register and by setting bit spclk of the spi mode register. pc4/sck is configured as input clock (slave mode) by programming it as input through ddrc register and by clearing bit spclk of the spi mode regis - ter. with this configuration, pc4 can simultaneous - ly be used as an input.
41/79 ST62T55CM-AUTO st62t65cm-auto i/o ports (cont?d) figure 24peripheral interface configuration of spi, timer 1 and ar timer mux 1 0 dr pp/od out in clock in spi dr dr 0 1 mux in out timer 1 dr mux 1 0 dr or ar timer artimout artimin pwmoe pp/od pc3/sout pc2/sin pc4/sck pc1/tim1 artimin artimout vr0c1661 v dd b0 register misc. 0 1 clock out spclk mod register mux or or dr or tout
42/79 ST62T55CM-AUTO st62t65cm-auto 4.2 timer the mcu features an on-chip timer peripheral, consisting of an 8-bit counter with a 7-bit program - mable prescaler, giving a maximum count of 2 15 . the peripheral may be configured in three different operating modes. figure 25 shows the timer block diagram. the external timer pin is available to the user. the content of the 8-bit counter can be read/written in the timer/counter register, tcr, while the state of the 7-bit prescaler can be read in the psc register. the control logic device is managed in the tscr register as described in the following paragraphs. the 8-bit counter is decremented by the output (rising edge) coming from the 7-bit prescaler and can be loaded and read under program control. when it decrements to zero then the tmz (timer zero) bit in the tscr is set to ?1?. if the eti (ena - ble timer interrupt) bit in the tscr is also set to ?1?, an interrupt request is generated as described in the interrupt chapter. the timer interrupt can be used to exit the mcu from wait mode. the prescaler input can be the internal frequency f int divided by 12 or an external clock applied to the timer pin. the prescaler decrements on the rising edge. depending on the division factor pro - grammed by ps2, ps1 and ps0 bits in the tscr. the clock input of the timer/counter register is mul - tiplexed to different sources. for division factor 1, the clock input of the prescaler is also that of timer/ counter; for factor 2, bit 0 of the prescaler register is connected to the clock input of tcr. this bit changes its state at half the frequency of the pres - caler input clock. for factor 4, bit 1 of the psc is connected to the clock input of tcr, and so forth. the prescaler initialize bit, psi, in the tscr regis - ter must be set to ?1? to allow the prescaler (and hence the counter) to start. if it is cleared to ?0?, all the prescaler bits are set to ?1? and the counter is inhibited from counting. the prescaler can be loaded with any value between 0 and 7fh, if bit psi is set to ?1?. the prescaler tap is selected by means of the ps2/ps1/ps0 bits in the control reg - ister. figure 26 illustrates the timer?s working principle. figure 25. timer block diagram databus 8 8 8 8 8-bit counter 6 5 4 3 2 1 0 psc status/control register b7 b6 b5 b4 b3 b2 b1 b0 tmz eti tout dout psi ps2 ps1 ps0 select 1 of 7 3 latch synchronization logic timer interrupt line va00009 : 12 f osc
43/79 ST62T55CM-AUTO st62t65cm-auto timer (cont?d) 4.2.1 timer operating modes there are three operating modes, which are se - lected by the tout and dout bits (see tscr register). these three modes correspond to the two clocks which can be connected to the 7-bit prescaler (f int 12 or timer pin signal), and to the output mode. 4.2.1.1 gated mode (tout = ?0?, dout = ?1?) in this mode the prescaler is decremented by the timer clock input (f int 12), but only when the signal on the timer pin is held high (allowing pulse width measurement). this mode is selected by clearing the tout bit in the tscr register to ?0? (i.e. as input) and setting the dout bit to ?1?. pc1 must be configured in input mode 4.2.1.2 event counter mode (tout = ?0?, dout = ?0?) in this mode, the timer pin is the input clock of the prescaler which is decremented on the rising edge. 4.2.1.3 output mode (tout = ?1?, dout = data out) the timer pin is connected to the dout latch, hence the timer prescaler is clocked by the pres - caler clock input (f int 12). the user can select the desired prescaler division ratio through the ps2, ps1, ps0 bits. when the tcr count reaches 0, it sets the tmz bit in the tscr. the tmz bit can be tested under program control to perform a timer function whenever it goes high. the low-to-high tmz bit transition is used to latch the dout bit of the tscr and trans - fer it to the timer pin. th is operating mode allows external signal generation on the timer pin. table 12. timer operating modes 4.2.2 timer interrupt when the counter register decrements to zero with the eti (enable timer interrupt) bit set to one, an interrupt request is generated as described in the interrupt chapter. when the counter decrements to zero, the tmz bit in the tscr register is set to one. figure 26. timer working principle tout dout timer pin timer function 0 0 input event counter 0 1 input gated input 1 0 output output ?0? 1 1 output output ?1? bit0 bit1 bit2 bit3 bit6 bit5 bit4 clock 7-bit prescaler 8-1 multiplexer 8-bit counter bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1 0 2 3 4 5 6 7 ps0 ps1 ps2 va00186
44/79 ST62T55CM-AUTO st62t65cm-auto timer (cont?d) 4.2.3 application notes the user can select the presence of an on-chip pull-up on the timer pin as option. tmz is set when the coun ter reaches zero; howev - er, it may also be set by writing 00h in the tcr register or by setting bit 7 of the tscr register. the tmz bit must be cleared by user software when servicing the timer interrupt to avoid unde - sired interrupts when leav ing the interrupt service routine. after reset, the 8-bit counter register is loaded with 0ffh, while the 7-bit prescaler is load - ed with 07fh, and the tscr register is cleared. this means that the timer is stopped (psi=?0?) and the timer interrupt is disabled. if the timer is programmed in output mode, the dout bit is transferred to the timer pin when tmz is set to one (by software or due to counter decrement). when tmz is high, the latch is trans - parent and dout is copied to the timer pin. when tmz goes low, dout is latched. a write to the tcr regist er will predominate over the 8-bit counter decrement to 00h function, i.e. if a write and a tcr register decrement to 00h occur simultaneously, the write will take precedence, and the tmz bit is not set until the 8-bit counter reaches 00h again. the values of the tcr and the psc registers can be read accurately at any time. 4.2.4 timer registers timer status control register (tscr) address: 0d4h ? read/write bit 7 = tmz : timer zero bit a low-to-high transition in dicates that the timer count register has decrement to zero. this bit must be cleared by user software before starting a new count. bit 6 = eti : enable timer interrupt when set, enables the timer interrupt request (vector #4). if eti=0 the timer interrupt is disabled. if eti=1 and tmz=1 an interrupt request is gener - ated. bit 5 = tout : timers output control when low, this bit selects the input mode for the timer pin. when high the output mode is select - ed. bit 4 = dout : data output data sent to the timer output when tmz is set high (output mode only). input mode selection (input mode only). bit 3 = psi : prescaler initialize bit used to initialize the prescaler and inhibit its count - ing. when psi=?0? the prescaler is set to 7fh and the counter is inhibited. when psi=?1? the prescal - er is enabled to count downwards. as long as psi=?0? both counter and prescaler are not run - ning. bit 2, 1, 0 = ps2, ps1, ps0 : prescaler mux. se - lect. these bits select the division ratio of the pres - caler register. table 13prescaler division factors timer counter register tcr address: 0d3h ? read/write bit 7-0 = d7-d0 : counter bits. prescaler register psc address: 0d2h ? read/write bit 7 = d7 : always read as "0". bit 6-0 = d6-d0 : prescaler bits. 7 0 tmz eti tout dout psi ps2 ps1 ps0 ps2 ps1 ps0 divided by 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 7 0 d7 d6 d5 d4 d3 d2 d1 d0 7 0 d7 d6 d5 d4 d3 d2 d1 d0
45/79 ST62T55CM-AUTO st62t65cm-auto 4.3 auto-reload timer the auto-reload timer (ar timer) on-chip pe - ripheral consists of an 8-bit timer/counter with compare and capt ure/reload capabilities and of a 7-bit prescaler with a clock multiplexer, enabling the clock input to be selected as f int , f int/3 or an external clock source. a mode control register, armc, two status control registers, arsc0 and arsc1, an output pin, artimout, and an input pin, artimin, allow the auto-reload timer to be used in 4 modes: ? auto-reload (pwm generation), ? output compare and reload on external event (pll), ? input capture and output compare for time meas - urement. ? input capture and output compare for period measurement. the ar timer can be used to wake the mcu from wait mode either with an internal or with an exter - nal clock. it also can be used to wake the mcu from stop mode, if used with an external clock signal connected to the artimin pin. a load reg - ister allows the program to read and write the counter on the fly. 4.3.1 ar timer description the ar counter is an 8-bit up-counter incre - mented on the input clock?s rising edge. the coun - ter is loaded from the reload/capture register, arrc, for auto-reload or capture operations, as well as for initialization. direct access to the ar counter is not possible; however, by reading or writing the arlr load register, it is possible to read or write the counter?s contents on the fly. the ar timer?s input clock can be either the inter - nal clock (from the oscillato r divider), the internal clock divided by 3, or the clock signal connected to the artimin pin. selection between these clock sources is effected by suitably programming bits cc0-cc1 of the arsc1 register. the output of the ar multiplexer feeds the 7-bit programmable ar prescaler, arpsc, whic h selects one of the 8 available taps of the prescaler, as defined by psc0-psc2 in the ar m ode control register. thus the division factor of the prescaler can be set to 2n (where n = 0, 1,..7). the clock input to the ar counter is enabled by the ten (timer enable) bit in the armc register. when ten is reset, the ar counter is stopped and the prescaler and counter contents are frozen. when ten is set, the ar counter runs at the rate of the selected clock source. the counter is cleared on system reset. the ar counter may also be initialized by writing to the arlr load register, which also causes an immediate copy of the value to be placed in the ar counter, regardless of whether the counter is run - ning or not. initialization of the counter, by either method, will also clear the arpsc register, where - upon counting will start from a known value. 4.3.2 timer operating modes four different operating modes are available for the ar timer: auto-reload mode with pwm generation. this mode allows a pulse width modulated signal to be generated on the artimout pin with minimum core processing overhead. the free running 8-bit counter is fed by the pres - caler?s output, and is incremented on every rising edge of the clock signal. when a counter overflow occurs, the counter is automatically reloaded with the contents of the re - load/capture register, arcc, and artimout is set. when the counter reaches the value con - tained in the compare register (arcp), artimout is reset. on overflow, the ovf flag of the arsc0 register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, ovie, in the mode control register (armc), is set. the ovf flag must be reset by the user software. when the counter reaches the compare value, the cpf flag of the arsc0 register is set and a com - pare interrupt request is generated, if the compare interrupt enable bit, cpie, in the mode control register (armc), is set. the interrupt service rou - tine may then adjust the pwm period by loading a new value into arcp. the cpf flag must be reset by user software. the pwm signal is generated on the artimout pin (refer to the block diagram). the frequency of this signal is controlled by the prescaler setting and by the auto-reload value present in the re - load/capture register, arrc. the duty cycle of the pwm signal is controlled by the compare reg - ister, arcp.
46/79 ST62T55CM-AUTO st62t65cm-auto auto-reload timer (cont?d) figure 27. ar timer block diagram data bus 8 8 8 compare 8 reload/capture data bus ar timer vr01660a 8 8 r s tcld ovie pwmoe ovf load artimout m synchro artimin sl0-sl1 int f pb6/ ar register ef register load ar u x f int /3 ar prescaler 7-bit cc0-cc1 ar counter 8-bit ar compare register ovf eie ef interrupt cpf cpie cpf drb7 ddrb7 pb7/ ps0-ps2 88
47/79 ST62T55CM-AUTO st62t65cm-auto auto-reload timer (cont?d) it should be not ed that the reload values will also affect the value and the resolution of the duty cycle of pwm output signal. to obtain a signal on arti - mout, the contents of the arcp register must be greater than the contents of the arrc register. the maximum available resolution for the arti - mout duty cycle is: resolution = 1/[256-(arrc)] where arrc is the content of the reload/capture register. the compare value loaded in the com - pare register, arcp, must be in the range from (arrc) to 255. the artc counter is initia lized by writing to the arrc register and by then setting the tcld (tim - er load) and the ten (timer clock enable) bits in the mode control register, armc. enabling and selection of the clock source is con - trolled by the cc0, cc1, sl0 and sl1 bits in the status control register, arsc1. the prescaler di - vision ratio is selected by the ps0, ps1 and ps2 bits in the arsc1 register. in auto-reload mode, any of the three available clock sources can be sele cted: internal clock, in - ternal clock divided by 3 or the clock signal present on the artimin pin. figure 28. auto-reload timer pwm function counter compare value reload register pwm output t t 255 000 vr001852 t high t low
48/79 ST62T55CM-AUTO st62t65cm-auto auto-reload timer (cont?d) capture mode with pwm generation . in this mode, the ar counter operates as a free running 8-bit counter fed by the prescaler output. the counter is incremented on every clock rising edge. an 8-bit capture operation from the counter to the arrc register is performed on every active edge on the artimin pin, when enabled by edge con - trol bits sl0, sl1 in the arsc1 register. at the same time, the external flag, ef, in the arsc0 register is set and an external interrupt request is generated if the external interrupt enable bit, eie, in the armc register, is set. the ef flag must be reset by user software. each artc overflow sets artimout, while a match between the counter and arcp (compare register) resets artimout and sets the compare flag, cpf. a compare interrupt request is generat - ed if the related compare interrupt enable bit, cpie, is set. a pwm signal is generated on arti - mout. the cpf flag must be reset by user soft - ware. the frequency of the generated signal is deter - mined by the prescaler setting. the duty cycle is determined by the arcp register. initialization and reading of the counter are identi - cal to the auto-reload mode (see previous descrip - tion). enabling and selection of clock sources is control - led by the cc0 and cc1 bits in the ar status con - trol register, arsc1. the prescaler division ratio is selected by pro - gramming the ps0, ps1 and ps2 bits in the arsc1 register. in capture mode, the allowed clock sources are the internal clock and the internal clock divided by 3; the external artimin input pin should not be used as a clock source. capture mode with reset of counter and pres - caler, and pwm generation. this mode is identi - cal to the previous one, with the difference that a capture condition also resets the counter and the prescaler, thus allowing easy measurement of the time between two captures (for input period meas - urement on the artimin pin). note: in this mode it is recommended not to change the artimer counter value from ffh to any other value by writing this value in the arrc register and setting the tlcd bit in the armc reg - ister. load on external input . the counter operates as a free running 8-bit counter fed by the prescaler. the count is incremented on every clock rising edge. each counter overflow sets the artimout pin. a match between the counter and arcp (compare register) resets the artimout pin and sets the compare flag, cpf. a compare interrupt request is generated if the related compare interrupt enable bit, cpie, is set. a pwm signal is generated on artimout. the cpf flag must be reset by user software. initialization of the counter is as described in the previous paragraph. in addition, if the external ar - timin input is enabled, an active edge on the input pin will copy the contents of the arrc register into the counter, whether the counter is running or not. notes : the allowed ar timer clock sources are the fol - lowing: the clock frequency should not be modified while the counter is counting, since the counter may be set to an unpredictable value. for instance, the multiplexer setting should not be modified while the counter is counting. loading of the counter by any means (by auto-re - load, through arlr, arrc or by the core) resets the prescaler at the same time. care should be taken when both the capture inter - rupt and the overflow interrupt are used. capture and overflow are asynchronous. if the capture oc - curs when the overflow interrupt flag, ovf, is high (between counter overflow and the flag being reset by software, in the interrupt routine), the ex - ternal interrupt flag, ef, may be cleared simul - taneusly without the interrupt being taken into ac - count. the solution consists in resetting the ovf flag by writing 06h in the arsc0 register. the value of ef is not affected by this operation. if an interrupt has occured, it will be proce ssed when the mcu exits from the interrupt routine (the second interrupt is latched). ar timer mode clock sources auto-reload mode f int , f int/3 , artimin capture mode f int , f int/3 capture/reset mode f int , f int/3 external load mode f int , f int/3
49/79 ST62T55CM-AUTO st62t65cm-auto auto-reload timer (cont?d) 4.3.3 ar timer registers ar mode control register (armc) address: d5h ? read/write reset status: 00h the ar mode control register armc is used to program the different operating modes of the ar timer, to enable the cl ock and to initialize the counter. it can be read and written to by the core and it is cleared on system reset (the ar timer is disabled). note: care should be taken when writing to the armc register while ar timer is running: if a pwm signal is being output while the armc regis - ter is overwritten with its previous value, artimout pin remains at its previous state for a programmed time equal to t high (refer to figure 28 ). then, a new count starts. bit 7 = tlcd : timer load bit. this bit, when set, will cause the contents of arrc register to be loaded into the counter and the contents of the prescaler register, arpsc, are cleared in order to initialize the timer before starting to count. this bit is write-only and any atte mpt to read it will yield a logical zero. bit 6 = ten : timer clock enable. this bit, when set, allows the timer to co unt. when cleared, it will stop the timer and freeze arpsc and artsc. bit 5 = pwmoe : pwm output enable. this bit, when set, enables the pwm output on the arti - mout pin. when reset, the pwm output is disabled. bit 4 = eie : external interrupt enable. this bit, when set, enables the external interrupt request. when reset, the external interrupt request is masked. if eie is set and the related flag, ef, in the arsc0 register is also set, an interrupt re - quest is generated. bit 3 = cpie : compare interrupt enable. this bit, when set, enables the compare interrupt request. if cpie is reset, the compare interrupt request is masked. if cpie is set and the related flag, cpf, in the arsc0 register is also set, an interrupt re - quest is generated. bit 2 = ovie : overflow interrupt . this bit, when set, enables the overflow interrupt request. if ovie is reset, the compare interrupt request is masked. if ovie is set and the related flag, ovf in the arsc0 register is also set, an interrupt request is generated. bit 1-0 = armc1-armc0 : mode control bits 1-0 . these are the operating mode control bits. the fol - lowing bit combinations w ill select the various op - erating modes: ar timer status/control registers arsc0 & arsc1. these registers contain the ar timer sta - tus information bits and also allow the program - ming of clock sources, active edge and prescaler multiplexer setting. arsc0 register bits 0,1 and 2 contain the interrupt flags of the ar timer. these bits are read normal - ly. each one may be reset by software. writing a one does not affect the bit value. ar status control register 0 (arsc0) address: d6h ? read/clear bits 7-3 = d7-d3 : unused bit 2 = ef : external interrupt flag. this bit is set by any active edge on the external artimin input pin. the flag is cleared by writing a zero to the ef bit. bit 1 = cpf : compare interrupt flag. this bit is set if the contents of the counter and the arcp regis - ter are equal. the flag is cleared by writing a zero to the cpf bit. bit 0 = ovf : overflow interrupt flag. this bit is set by a transition of the counter from ffh to 00h (overflow). the flag is clea red by writing a zero to the ovf bit. 7 0 tcld ten pwmoe eie cpie ovie armc1 armc0 armc1 armc0 operating mode 0 0 auto-reload mode 0 1 capture mode 1 0 capture mode with reset of artc and arpsc 1 1 load on external edge mode 7 0 d7 d6 d5 d4 d3 ef cpf ovf
50/79 ST62T55CM-AUTO st62t65cm-auto auto-reload timer (cont?d) ar status control register 1(arsc1) address: d7h ? read/write bist 7-5 = ps2-ps0 : prescaler division selection bits 2-0. these bits determine the prescaler divi - sion ratio. the prescaler itself is not affected by these bits. the prescaler division ratio is listed in the following table: table 14. prescaler division ratio selection bit 4 = d4 : reserved . must be kept reset. bit 3-2 = sl1-sl0 : timer input edge control bits 1- 0. these bits control the edge function of the timer input pin for external synchronization. if bit sl0 is re - set, edge detection is disabled; if set edge detection is enabled. if bit sl1 is reset, the ar timer input pin is rising edge sensitive; if set, it is falling edge sen - sitive. bit 1-0 = cc1-cc0 : clock source select bit 1-0. these bits select the clo ck source for the ar timer through the ar multiplexer. the programming of the clock sources is explained in the following table 15 : table 15. clock source selection. ar load register arlr . the arlr load register is used to read or write the artc counter register ?on the fly? (while it is counting). the arlr regis - ter is not affected by system reset. ar load register (arlr) address: dbh ? read/write bit 7-0 = d7-d0 : load register data bits. these are the load register data bits. ar reload/capture register . the arrc reload/ capture register is used to hold the auto-reload value which is automatica lly loaded into the coun - ter when overflow occurs. ar reload/capture (arrc) address: d9h ? read/write bit 7-0 = d7-d0 : reload/capture data bits . these are the reload/capture register data bits. ar compare register . the cp compare register is used to hold the compare value for the compare function. ar compare register (arcp) address: dah ? read/write bit 7-0 = d7-d0 : compare data bits . these are the compare register data bits. 7 0 ps2 ps1 ps0 d4 sl1 sl0 cc1 cc0 ps2 ps1 ps0 arpsc division ratio 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 2 4 8 16 32 64 128 sl1 sl0 edge detection x 0 disabled 0 1 rising edge 1 1 falling edge cc1 cc0 clock source 0 0 f int 0 1 f int divided by 3 1 0 artimin input clock 1 1 reserved 7 0 d7 d6 d5 d4 d3 d2 d1 d0 7 0 d7 d6 d5 d4 d3 d2 d1 d0 7 0 d7 d6 d5 d4 d3 d2 d1 d0
51/79 ST62T55CM-AUTO st62t65cm-auto 4.4 a/d converter (adc) the a/d converter peripheral is an 8-bit analog to digital converter with analog inputs as alternate i/o functions (the number of which is device depend - ent), offering 8-bit resolution with a typical conver - sion time of 70us (at an oscillator clock frequency of 8mhz). the adc converts the input voltage by a process of successive approximations, using a clock fre - quency derived from the os cillator with a division factor of twelve. with an oscillator clock frequency less than 1.2mhz, conversion accuracy is de - creased. selection of the input pin is done by configuring the related i/o line as an analog input via the op - tion and data registers (refer to i/o ports descrip - tion for additional inform ation). only one i/o line must be configured as an analog input at any time. the user must avoid any situation in which more than one i/o pin is selected as an analog input si - multaneously, to avoid device malfunction. the adc uses two registers in the data space: the adc data conversion register, adr, which stores the conversion result, and the adc control regis - ter, adcr, used to pr ogram the adc functions. a conversion is started by writing a ?1? to the start bit (sta) in the adc control register. this auto - matically clears (resets to ?0?) the end of conver - sion bit (eoc). when a conversion is complete, the eoc bit is automatically set to ?1?, in order to flag that conversion is complete and that the data in the adc data conversion register is valid. each conversion has to be separa tely initiated by writing to the sta bit. the sta bit is continuously scanned so that, if the user sets it to ?1? while a previous conversion is in progress, a new conversion is started before com - pleting the previous one. the start bit (sta) is a write only bit, any attempt to read it will show a log - ical ?0?. the a/d converter features a maskable interrupt associated with the end of conversion. this inter - rupt is associated with interrupt vector #4 and oc - curs when the eoc bit is set (i.e. when a conver - sion is completed). the interrupt is masked using the eai (interrupt mask) bit in the control register. the power consumption of the device can be re - duced by turning off the adc peripheral. this is done by setting the pds bit in the adc control reg - ister to ?0?. if pds=?1?, the a/d is powered and en - abled for conversion. this bit must be set at least one instruction before the beginning of the conver - sion to allow stabilisatio n of the a/d converter. this action is also needed before entering wait mode, since the a/d comparator is not automati - cally disabled in wait mode. during reset, any conversion in progress is stopped, the control register is reset to 40h and the adc interrupt is masked (eai=0). figure 29. adc block diagram 4.4.1 application notes the a/d converter does not feature a sample and hold circuit. the analog voltage to be measured should therefore be stable during the entire con - version cycle. voltage variation should not exceed 1/2 lsb for the optimu m conversion accuracy. a low pass filter may be used at the analog input pins to reduce input voltage variation during con - version. when selected as an analog channel, the input pin is internally connected to a capacitor c ad of typi - cally 12pf. for maximum accuracy, this capacitor must be fully charged at the beginning of conver - sion. in the worst case, conversion starts one in - struction (6.5 s) after the channel has been se - lected. in worst case conditions, the impedance, asi, of the analog voltage source is calculated us - ing the following formula: 6.5s = 9 x c ad x asi (capacitor charged to over 99.9%), i.e. 30 k ? in - cluding a 50% guardband. asi can be higher if c ad has been charged for a longer period by adding in - structions before the start of conversion (adding more than 26 cpu cycles is pointless). control register converter va00418 result register reset interrupt clock av av dd ain 8 core control signals ss 8 core
52/79 ST62T55CM-AUTO st62t65cm-auto a/d converter (cont?d) since the adc is on the same chip as the micro - processor, the user should not switch heavily load - ed output signals during conversion, if high preci - sion is required. such s witching will affect the sup - ply voltages used as analog references. the accuracy of the conversion depends on the quality of the power supplies (v dd and v ss ). the user must take special care to ensure a well regu - lated reference voltage is present on the v dd and v ss pins (power supply voltage variations must be less than 5v/ms). this imp lies, in particular, that a suitable decoupling capacitor is used at the v dd pin. the converter resolution is given by:: the input voltage (ain) which is to be converted must be constant for 1s before conversion and remain constant during conversion. conversion resolution can be improved if the pow - er supply voltage (v dd ) to the microcontroller is lowered. in order to optimise conversion resolution, the user can configure the microcontroller in wait mode, because this mode minimises noise disturbances and power supply variations due to output switch - ing. nevertheless, the wait instruction should be executed as soon as possible after the beginning of the conversion, because execution of the wait instruction may cause a sm all variation of the v dd voltage. the negative effect of this variation is min - imized at the beginning of the conversion when the converter is less sensitive, rather than at the end of conversion, when the less significant bits are determined. the best configuration, from an accuracy stand - point, is wait mode with the timer stopped. in - deed, only the adc perip heral and the oscillator are then still working. the mcu must be woken up from wait mode by the adc interrupt at the end of the conversion. it should be noted that waking up the microcontroller could also be done using the timer interrupt, but in this case the timer will be working and the resulting noise could affect conversion accuracy. one extra feature is available in the adc to get a better accuracy. in fact, each adc conversion has to be followed by a wait instruction to minimize the noise during the conversion. but the first con - version step is performed before the execution of the wait when most of cl ocks signals are still en - abled . the key is to synchronize the adc start with the effective execution of the wait. this is achieved by setting adc sync option. this way, adc conversion starts in effective wait for maxi - mum accuracy. note: with this extra option, it is mandatory to ex - ecute wait instruction just after adc start instruc - tion. insertion of any extra instruction may cause spurious interrupt request at adc interrupt vector. a/d converter control register (adcr) address: 0d1h ? read/write bit 7 = eai : enable a/d interrupt. if this bit is set to ?1? the a/d interrupt is enabled, when eai=0 the interrupt is disabled. bit 6 = eoc : end of conversion. read only . this read only bit indicates when a conversion has been completed. this bit is automatically reset to ?0? when the sta bit is written. if the user is using the interrupt option then this bit can be used as an interrupt pending bit. data in the data conversion register are valid only when this bit is set to ?1?. bit 5 = sta : start of conversion. write only . writ - ing a ?1? to this bit will start a conversion on the se - lected channel and automatically reset to ?0? the eoc bit. if the bit is set again when a conversion is in progress, the present conversion is stopped and a new one will take place. this bit is write only, any attempt to read it will show a logical zero. bit 4 = pds : power down selection. this bit acti - vates the a/d converter if set to ?1?. writing a ?0? to this bit will put the adc in power down mode (idle mode). bit 3-0 = d3-d0. not used a/d converter data register (adr) address: 0d0h ? read only bit 7-0 = d7-d0 : 8 bit a/d conversion result. v dd v ss ? 256 --------------------------- - 7 0 eai eoc sta pds d3 d2 d1 d0 7 0 d7 d6 d5 d4 d3 d2 d1 d0
53/79 ST62T55CM-AUTO st62t65cm-auto 4.5 serial peripheral interface (spi) the spi peripheral is an optimized synchronous serial interface with programmable transmission modes and master/slave capabilities supporting a wide range of industry standard spi specifications. the spi interface may also implement asynchro - nous data transfer, in which case processor over - head is limited to data transfer from or to the shift register on an interrupt driven basis. the spi may be controlled by simple user soft - ware to perform serial data exchange with low- cost external memory, or with serially controlled peripherals to drive displays, motors or relays. the spi?s shift register is simultaneously fed by the sin pin and feeds the sout pin, thus transmis - sion and reception are essentially the same proc - ess. suitable setting of the number of bits in the data frame can allow filtering of unwanted leading data bits in the incoming data stream. the spi comprises an 8-bit data/shift register, dsr, a divide register, div, a mode control reg - ister mod, and a miscellaneous register, miscr. the spi may be operated either in master mode or in slave mode. master mode is defined by the synchronous serial clock being supplied by the mcu, by suitably pro - gramming the clock divider (div register). slave mode is defined by the serial clock being supplied externally on the sck pin by the external master device. for maximum versatility the spi may be pro - grammed to sample data either on the rising or on the falling edge of sck, wit h or without phase shift (clock polarity and phase selection). the sin, sout and sck signals are connected as alternate i/o pin functions. for serial input operation, sin must be configured as an input. for serial output operation, sout is se - lected as an output by programming bit 0 of the miscellaneous register: clearing this bit will set the pin as a standard i/o line, while setting the bit will select the sout function. an interrupt request may be associated with the end of a transmission or reception cycle; this is de - fined by programming the number of bits in the data frame and by enabling the interrupt. this re - quest is associated with interrupt vector #2, and can be masked by programming the spie bit of the mod register. since the spi interrupt is ?ored? with the port interrupt source, an interrupt flag bit is available in the div register allowing dis - crimination of the interrupt request. figure 30. spi block diagram spi sck filter sin sout cpu cycle clock clock data bus 8 vr001693 shift register filter divider
54/79 ST62T55CM-AUTO st62t65cm-auto serial peripheral interface spi (cont?d) 4.5.1 spi registers spi mode control register (mod) address: e2h ? read/write reset status: 00h the mod register defines and controls the trans - mission modes and characteristics. this register is read/write and all bits are cleared at reset. setting spstrt = 1 and spin = 1 is not allowed and must be avoided. bit 7 = sprun : spi run . this bit is the spi activity flag. this can be used in either transmit or receive modes; it is automatically cleared by the spi at the end of a transmission or reception and generates an interrupt request (providing that the spie inter - rupt enable bit is set). the core can stop transmis - sion or reception at any time by resetting the sprun bit; this will also generate an interrupt re - quest (providing that the spie interrupt enable bit is set). the sprun bit can be used as a start con - dition parameter, in co njunction with the spstrt bit, when an external si gnal is present on the sin pin. note that a rising edge is then necessary to in - itiate reception; this may require external data in - version. this bit can be used to poll the end of re - ception or transmission. bit 6 = spie : spi interrupt enable . this bit is the spi interrupt enable bit. if this bit is set the spi in - terrupt (vector #2) is enabled, when spie is reset, the interrupt is disabled. bit 5 = cpha : clock phase selection . this bit se - lects the clock phase of the clock signal. if this bit is cleared to zero the no rmal state is selected; in this case bit 7 of the data frame is present on sout pin as soon as the spi shi ft register is loaded. if this bit is set to one the shifted state' is selected; in this case bit 7 of data frame is present on sout pin on the first falling edge of shift register clock. the polarity relation and the division ratio between shift register and spi base clock are also pro - grammable; refer to div register and timing dia - grams for more information. bit 4= spclk : base clock selection this bit selects the spi base clock source. it is ei - ther the core cycle clock (f int /13) (master mode) or the signal provided at sck pin by an external device (slave mode). if spclk is low and the sck pin is configured as input, the slave mode is se - lected. if spclk is high, the sck pin is automatic - cally configured as push pull output and the mas - ter mode is selected. in this case, the phase and polarity of the clock are controlled by cpol and cpha. note : when the master mode is enabled, it is mandatory to configure pc4 in input mode through the i/o port registers. bit 3 = spin : input selection this bit enables the transfer of the data input to the shift register in receive mode. if this bit is cleared the shift register input is 0. if this bit is set, the shift register input corresponds to the input signal present on the sin pin. bit 2 = spstrt : start selection this bit selects the transmission or reception start mode. if spstrt is cleared, the internal start con - dition occurs as soon as the sprun bit is set. if spstrt is set, the internal start signal is the logic ?and? between the sprun bit and the external signal present on the sin pin; in this case transmis - sion will start after the late st of both signals provid - ing that the first signal is still present (not e that this implies a rising edge). after the transmission or re - cetion has been started, it will continue even if the sin signal is reset. bit 1 = efilt : enable filters this bit enables/disables the input noise filters on the sin and sck inputs. if it is cleared to zero the filters are enabled, if set to one the filters are disa - bled. these noise filters will eliminate any pulse on sin and sck with a pulse width smaller than one to two core clock periods (depending on the oc - currence of the signal edge with respect to the core clock edge). for example, if the st6260b/ 65b runs with an 8mhz crystal, sin and sck will be delayed by 125 to 250ns. bit 0 = cpol : clock polarity this bit controls the relationship between the data on the sin and sout pins and sck. the cpol bit selects the clock edge which captures data and al - lows it to change state. it has the greatest impact on the first bit transmitted (the msb) as it does (or does not) allow a clock transition before the first data capture edge. refer to the timing diagrams at the end of this sec - tion for additional details. these show the relation - ship between cpol, cpha and sck, and indicate the active clock edges and strobe times. 7 0 sprun spie cpha spclk spin spstrt efilt cpol
55/79 ST62T55CM-AUTO st62t65cm-auto serial peripheral interface spi (cont?d) spi div register (div) address: e1h ? read/write reset status: 00h the spidiv register defines the transmission rate and frame format and contains the interrupt flag. bits cd0-cd2, div3-div6 are read/write while spint can be read and cleared only. write access is not allowed if sprun in the mod register is set. bit 7 = spint : interrupt flag. if spie bit=1, spint is automatically set to one by the spi at the end of a transmission or reception and an interrupt re - quest can be generated depending on the state of the interrupt mask bit in the mod control register. this bit is write and read and must be cleared by user software at the end of the interrupt service routine. bit 6-3 = div6-div3 : burst mode bit clock period selection. define the number of shift register bits that are transmitted or received in a frame. the available selections are listed in table 17 . the normal maximum setting is 8 bits, since the shift register is 8 bits wide. note that by setting a great - er number of bits, in conjunction with the spin bit in the mod register, unwanted data bits may be fil - tered from the data stream. bit 2-0 = cd2-cd0 : base/bit clock rate selec - tion . define the division ratio between the core clock (f int divided by 13) and the clock supplied to the shift register in master mode. table 16. base/bit clock ratio selection note : for example, when an 8mhz cpu clock is used, asynchronous operation at 9600 baud is possible (8mhz/13/64). other baud rates are available by proportionally selecting division fac - tors depending on cpu clock frequency. data setup time on sin is typically 250ns min, while data hold time is typically 50ns min. spi data/shift register (spidsr) address: e0h ? read/write reset status: xxh spidsr is read/write, however write access is not allowed if the sprun bit of mode control register is set to one. data is sampled into spdsr on the sck edge de - termined by the cpol and cpha bits. the affect of these setting is shown in the following diagrams. the shift register transmits and receives the most significant bit first. bit 7-0 = dsr7-dsr0 : data bits. these are the spi shift register data bits. miscellaneous register (miscr) address: ddh ? write only reset status: xxxxxxxb bit 7-1 = d7-d1 : reserved. bit 0 = d0 : bit 0. this bit, when set, selects the sout pin as the spi output line. when this bit is cleared, sout acts as a standard i/o line. 7 0 spint dov6 div5 div4 div3 cd2 cd1 cd0 cd2-cd0 divide ratio (decimal) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 divide by 1 divide by 2 divide by 4 divide by 8 divide by 16 divide by 32 divide by 64 divide by 256 div6-div3 number of bits sent 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 reserved (not to be used) 1 2 3 4 5 6 7 8 9 ? 10 ? 11 ? refer to the 12 ? description of the 13 ? div6-div3 bits in 14 ? the div register 15 ? 7 0 d7 d6 d5 d4 d3 d2 d1 d0 7 0 - - - - - - - d0
56/79 ST62T55CM-AUTO st62t65cm-auto serial peripheral interface spi (cont?d) 4.6 spi timing diagrams figure 31. cpol = 0 clock polarity no rmal, cpha = 0 phase selection normal figure 32. cpol = 1 clock polarity inverted, cpha = 0 phase selection normal sprun sout sin b7 b6 b5 b4 b3 b2 b1 b0 vr001694 sck sampling sprun sck sout sin b7 b6 b5 b4 b3 b2 b1 b0 vr0a1694 sampling
57/79 ST62T55CM-AUTO st62t65cm-auto serial peripheral interface spi (cont?d) figure 33. cpol = 0 clock polarity normal, cpha = 1 phase selection shifted figure 34. cpol = 1 clock polarity inverted, cpha = 1 phase selection shifted sprun sck sout b7 b6 b5 b4 b3 b2 b1 b0 vr0b1694 sin sampling sprun sck sout b7 b6 b5 b4 b3 b2 b1 b0 vr0c1694 sin sampling
58/79 ST62T55CM-AUTO st62t65cm-auto 5 software 5.1 st6 architecture the st6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. the st6 core has the abilit y to set or clear any register or ram location bit of the data space with a single instruction. furthermore, the program may branch to a selected address depending on the status of any bit of the data space. the carry bit is stored with the value of the bit when the set or res instruction is processed. 5.2 addressing modes the st6 core offers nine addressing modes, which are described in the following paragraphs. three different address spaces are available: pro - gram space, data space, and stack space. pro - gram space contains the instructions which are to be executed, plus the data for immediate mode in - structions. data space contains the accumulator, the x,y,v and w registers, peripheral and input/ output registers, the ram locations and data rom locations (for storage of tables and con - stants). stack space contains six 12-bit ram cells used to stack the return addresses for subroutines and interrupts. immediate . in the immediate addressing mode, the operand of the instruction follows the opcode location. as the operand is a rom byte, the imme - diate addressing mode is used to access con - stants which do not change during program execu - tion (e.g., a constant used to initialize a loop coun - ter). direct . in the direct addressing mode, the address of the byte which is processed by the instruction is stored in the location which follows the opcode. di - rect addressing allows the user to directly address the 256 bytes in data space memory with a single two-byte instruction. short direct . the core can address the four ram registers x,y,v,w (locations 80h, 81h, 82h, 83h) in the short-direct addressing mode. in this case, the instruction is only one byte and the selection of the location to be processed is contained in the op - code. short direct addressing is a subset of the di - rect addressing mode. (note that 80h and 81h are also indirect registers). extended . in the extended addressing mode, the 12-bit address needed to define the instruction is obtained by concatenating the four less significant bits of the opcode with the byte following the op - code. the instructions (jp, call) which use the extended addressing mode are able to branch to any address of the 4k bytes program space. an extended addressing mode instruction is two- byte long. program counter relative . the relative address - ing mode is only used in conditional branch in - structions. the instruction is used to perform a test and, if the condition is true, a branch with a span of -15 to +16 locations around the address of the rel - ative instruction. if the co ndition is not true, the in - struction which follows the relative instruction is executed. the relative addressing mode instruc - tion is one-byte long. the opcode is obtained in adding the three most significant bits which char - acterize the kind of the test, one bit which deter - mines whether the branch is a forward (when it is 0) or backward (when it is 1) branch and the four less significant bits which give the span of the branch (0h to fh) which must be added or sub - tracted to the address of the relative instruction to obtain the address of the branch. bit direct . in the bit direct addressing mode, the bit to be set or cleared is part of the opcode, and the byte following the opcode points to the ad - dress of the byte in which the specified bit must be set or cleared. thus, any bit in the 256 locations of data space memory can be set or cleared. bit test & branch . the bit test and branch ad - dressing mode is a combination of direct address - ing and relative addressing. the bit test and branch instruction is three-byte long. the bit iden - tification and the tested condition are included in the opcode byte. the address of the byte to be tested follows immediately the opcode in the pro - gram space. the third byte is the jump displace - ment, which is in the range of -127 to +128. this displacement can be determined using a label, which is converted by the assembler. indirect . in the indirect addressing mode, the byte processed by the register-indirect instruction is at the address pointed by the content of one of the in - direct registers, x or y (80h,81h). the indirect reg - ister is selected by the bit 4 of the opcode. a regis - ter indirect instructio n is one byte long. inherent . in the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. these instructions are one byte long.
59/79 ST62T55CM-AUTO st62t65cm-auto 5.3 instruction set the st6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. they can be di - vided into six different types: load/store, arithme - tic/logic, conditional bran ch, control instructions, jump/call, and bit manipulation. the following par - agraphs describe the different types. all the instructions belonging to a given type are presented in individual tables. load & store . these instructions use one, two or three bytes in relation with the addressing mode. one operand is the accumulator for load and the other operand is obtained from data memory using one of the addressing modes. for load immediate one operand can be any of the 256 data space bytes while the other is always immediate data. table 18. load & store instructions notes: x,y. indirect register pointers, v & w short direct registers # . immediate data (stored in rom memory) rr. data space register ? . affected * . not affected instruction addressing mode bytes cycles flags z c ld a, x short direct 1 4 ? * ld a, y short direct 1 4 ? * ld a, v short direct 1 4 ? * ld a, w short direct 1 4 ? * ld x, a short direct 1 4 ? * ld y, a short direct 1 4 ? * ld v, a short direct 1 4 ? * ld w, a short direct 1 4 ? * ld a, rr direct 2 4 ? * ld rr, a direct 2 4 ? * ld a, (x) indirect 1 4 ? * ld a, (y) indirect 1 4 ? * ld (x), a indirect 1 4 ? * ld (y), a indirect 1 4 ? * ldi a, #n immediate 2 4 ? * ldi rr, #n immediate 3 4 * *
60/79 ST62T55CM-AUTO st62t65cm-auto instruction set (cont?d) arithmetic and logic . these instructions are used to perform the arithmetic calculations and logic operations. in and, add, cp, sub instruc - tions one operand is always the accumulator while the other can be either a data space memory con - tent or an immediate value in relation with the ad - dressing mode. in clr, dec, inc instructions the operand can be any of the 256 data space ad - dresses. in com, rlc, sla the operand is always the accumulator. table 19. arithmetic & logic instructions notes: x,y.indirect register pointers, v & w short direct registersd. affected # . immediate data (stored in rom memory)* . not affected rr. data space register instruction addressing mode bytes cycles flags z c add a, (x) indirect 1 4 ? ? add a, (y) indirect 1 4 ? ? add a, rr direct 2 4 ? ? addi a, #n immediate 2 4 ? ? and a, (x) indirect 1 4 ? ? and a, (y) indirect 1 4 ? ? and a, rr direct 2 4 ? ? andi a, #n immediate 2 4 ? ? clr a short direct 2 4 ? ? clr r direct 3 4 * * com a inherent 1 4 ? ? cp a, (x) indirect 1 4 ? ? cp a, (y) indirect 1 4 ? ? cp a, rr direct 2 4 ? ? cpi a, #n immediate 2 4 ? ? dec x short direct 1 4 ? * dec y short direct 1 4 ? * dec v short direct 1 4 ? * dec w short direct 1 4 ? * dec a direct 2 4 ? * dec rr direct 2 4 ? * dec (x) indirect 1 4 ? * dec (y) indirect 1 4 ? * inc x short direct 1 4 ? * inc y short direct 1 4 ? * inc v short direct 1 4 ? * inc w short direct 1 4 ? * inc a direct 2 4 ? * inc rr direct 2 4 ? * inc (x) indirect 1 4 ? * inc (y) indirect 1 4 ? * rlc a inherent 1 4 ? ? sla a inherent 2 4 ? ? sub a, (x) indirect 1 4 ? ? sub a, (y) indirect 1 4 ? ? sub a, rr direct 2 4 ? ? subi a, #n immediate 2 4 ? ?
61/79 ST62T55CM-AUTO st62t65cm-auto instruction set (cont?d) conditional branch . the branch instructions achieve a branch in the program when the select - ed condition is met. bit manipulation instructions . these instruc - tions can handle any bit in data space memory. one group either sets or clears. the other group (see conditional branch) performs the bit test branch operations. control instructions . the control instructions control the mcu operations during program exe - cution. jump and call. these two instructions are used to perform long (12-bit) jumps or subroutines call inside the whole program space. table 20. conditional branch instructions notes : b. 3-bit address rr. data space register e. 5 bit signed displacement in the range -15 to +16 ? . affected. the tested bit is shifted into carry. ee. 8 bit signed displacement in the range -126 to +129 * . not affected table 21. bit manipulation instructions notes: b. 3-bit address; * . not affected rr. data space register; table 22. control instructions notes: 1. this instruction is deactivatedand a wait is automatically executed instead of a stop if the watchdog function is selected . ? . affected *. not affected table 23. jump & call instructions notes: abc. 12-bit address; * . not affected instruction branch if bytes cycles flags z c jrc e c = 1 1 2 * * jrnc e c = 0 1 2 * * jrz e z = 1 1 2 * * jrnz e z = 0 1 2 * * jrr b, rr, ee bit = 0 3 5 * ? jrs b, rr, ee bit = 1 3 5 * ? instruction addressing mode bytes cycles flags z c set b,rr bit direct 2 4 * * res b,rr bit direct 2 4 * * instruction addressing mode bytes cycles flags z c nop inherent 1 2 * * ret inherent 1 2 * * reti inherent 1 2 ? ? stop (1) inherent 1 2 * * wait inherent 1 2 * * instruction addressing mode bytes cycles flags z c call abc extended 2 4 * * jp abc extended 2 4 * *
62/79 ST62T55CM-AUTO st62t65cm-auto opcode map summary. the following table contains an opcode map for the instructions used by the st6 low 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 low hi hi 0 0000 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 ld 0 0000 e abc e b0,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 1 0001 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 inc 2 jrc 4 ldi 1 0001 e abc e b0,rr,ee e x e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 2 0010 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 cp 2 0010 e abc e b4,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 3 0011 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 4 cpi 3 0011 e abc e b4,rr,ee e a,x e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 4 0100 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 add 4 0100 e abc e b2,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 5 0101 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 inc 2 jrc 4 addi 5 0101 e abc e b2,rr,ee e y e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 6 0110 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 inc 6 0110 e abc e b6,rr,ee e # e (x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 7 0111 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 7 0111 e abc e b6,rr,ee e a,y e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 8 1000 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 ld 8 1000 e abc e b1,rr,ee e # e (x),a 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 9 1001 2 rnz 4 call 2 jrnc 5 jrs 2 jrz 4 inc 2 jrc 9 1001 e abc e b1,rr,ee e v e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc a 1010 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 and a 1010 e abc e b5,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind b 1011 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 4 andi b 1011 e abc e b5,rr,ee e a,v e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm c 1100 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 sub c 1100 e abc e b3,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind d 1101 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 inc 2 jrc 4 subi d 1101 e abc e b3,rr,ee e w e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm e 1110 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 dec e 1110 e abc e b7,rr,ee e # e (x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind f 1111 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc f 1111 e abc e b7,rr,ee e a,w e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc abbreviations for addressing modes: legend: dir direct # indicates illegal instructions sd short direct e 5 bit displacement imm immediate b 3 bit address inh inherent rr 1byte dataspace address ext extended nn 1 byte immediate data b.d bit direct abc 12 bit address bt bit test ee 8 bit displacement pcr program counter relative ind indirect 2 jrc e 1prc mnemonic addressing mode bytes cycle operand
63/79 ST62T55CM-AUTO st62t65cm-auto opcode map summary (continued) low 8 1000 9 1001 a 1010 b 1011 c 1100 d 1101 e 1110 f 1111 low hi hi 0 0000 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 ldi 2 jrc 4 ld 0 0000 e abc e b0,rr e rr,nn e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 3 imm 1 prc 1 ind 1 0001 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 ld 1 0001 e abc e b0,rr e x e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 2 0010 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 com 2 jrc 4 cp 2 0010 e abc e b4,rr e a e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind 3 0011 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 ld 2 jrc 4 cp 3 0011 e abc e b4,rr e x,a e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 4 0100 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 reti 2 jrc 4 add 4 0100 e abc e b2,rr e e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind 5 0101 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 add 5 0101 e abc e b2,rr e y e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 6 0110 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 stop 2 jrc 4 inc 6 0110 e abc e b6,rr e e (y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind 7 0111 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 ld 2 jrc 4 inc 7 0111 e abc e b6,rr e y,a e rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 8 1000 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 jrc 4 ld 8 1000 e abc e b1,rr e # e (y),a 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind 9 1001 2 rnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 ld 9 1001 e abc e b1,rr e v e rr,a 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir a 1010 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 rcl 2 jrc 4 and a 1010 e abc e b5,rr e a e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind b 1011 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 ld 2 jrc 4 and b 1011 e abc e b5,rr e v,a e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir c 1100 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 ret 2 jrc 4 sub c 1100 e abc e b3,rr e e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind d 1101 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 sub d 1101 e abc e b3,rr e w e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir e 1110 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 wait 2 jrc 4 dec e 1110 e abc e b7,rr e e (y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind f 1111 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 ld 2 jrc 4 dec f 1111 e abc e b7,rr e w,a e rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir abbreviations for addressing modes: legend: dir direct # indicates illegal instructions sd short direct e 5 bit displacement imm immediate b 3 bit address inh inherent rr 1byte dataspace address ext extended nn 1 byte immediate data b.d bit direct abc 12 bit address bt bit test ee 8 bit displacement pcr program counter relative ind indirect 2 jrc e 1prc mnemonic addressing mode bytes cycle operand
64/79 ST62T55CM-AUTO st62t65cm-auto 6 electrical characteristics 6.1 absolute maximum ratings this product contains devices to protect the inputs against damage due to high static voltages, how - ever it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. for proper operation it is recommended that v i and v o be higher than v ss and lower than v dd . reliability is enhanced if unused inputs are con - nected to an appropriate logic voltage level (v dd or v ss ). power considerations .the average chip-junc - tion temperature, tj, in celsius can be obtained from: tj=ta + pd x rthja where:ta = ambient temperature. rthja =package thermal resistance (junc - tion-to ambient). pd = pint + pport. pint =idd x vdd (chip internal power). pport =port power dissipation (determined by the user). notes: - stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating o nly and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended perio ds may affect device reliability. - (1) within these limits, clamping diodes are guarantee to be not conductive. voltages outside these limits are authorised as long as injection current is kept within the specification. symbol parameter value unit v dd supply voltage -0.3 to 7.0 v v i input voltage v ss - 0.3 to v dd + 0.3 (1) v v o output voltage v ss - 0.3 to v dd + 0.3 (1) v iv dd total current into v dd (source) 80 ma iv ss total current out of v ss (sink) 100 ma tj junction temperature 150 c t stg storage temperature -60 to 150 c
65/79 ST62T55CM-AUTO st62t65cm-auto 6.2 recommended operating conditions notes : 1. care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the a/d conversion. for a -1ma injection, a maximum 10 k ? is recommended. 2.an oscillator frequency above 1mhz is recommended for reliable a/d results figure 35. maximum operating frequenc y (fmax) versus supply voltage (v dd ) the shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions. symbol parameter test conditions value unit min. typ. max. t a operating temperature 6 suffix version 1 suffix version 3 suffix version -40 0 -40 85 70 125 c v dd operating supply voltage (except st626xb rom devices) f osc = 4mhz, 1 & 6 suffix f osc = 4mhz, 3 suffix fosc= 8mhz , 1 & 6 suffix fosc= 8mhz , 3 suffix 3.0 3.0 3.6 4.5 6.0 6.0 6.0 6.0 v operating supply voltage (st626xb rom devices) f osc = 4mhz, 1 & 6 suffix f osc = 4mhz, 3 suffix fosc= 8mhz , 1 & 6 suffix fosc= 8mhz , 3 suffix 3.0 3.0 4.0 4.5 6.0 6.0 6.0 6.0 v f osc oscillator frequency 2) (except st626xb rom devices) v dd = 3.0v, 1 & 6 suffix v dd = 3.0v , 3 suffix v dd = 3.6v , 1 & 6 suffix v dd = 3.6v , 3 suffix 0 0 0 0 4.0 4.0 8.0 4.0 mhz oscillator frequency 2) (st626xb rom devices) v dd = 3.0v, 1 & 6 suffix v dd = 3.0v , 3 suffix v dd = 4.0v , 1 & 6 suffix v dd = 4.0v , 3 suffix 0 0 0 0 4.0 4.0 8.0 4.0 mhz i inj+ pin injection current (positive) v dd = 4.5 to 5.5v +5 ma i inj- pin injection current (negative) v dd = 4.5 to 5.5v -5 ma 8 7 6 5 4 3 2 1 2.5 3 44.5 55.5 6 supply voltage (v dd ) maximum frequency (mhz) functionality is not guaranteed in this area 3 suffix version 1 & 6 suffix version 3.6 3 suffix version st626xb rom devices all devices except st626xb rom devices 1 & 6 suffix version
66/79 ST62T55CM-AUTO st62t65cm-auto 6.3 dc electrical characteristics (t a = -40 to +125c unless otherwise specified) notes: (1) hysteresis voltage between switching levels (2) all peripherals running (3) all peripherals in stand-by symbol parameter test conditions value unit min. typ. max. v il input low level voltage all input pins v dd x 0.3 v v ih input high level voltage all input pins v dd x 0.7 v v hys hysteresis voltage (1) all input pins v dd = 5v v dd = 3v 0.2 0.2 v v up lvd threshold in power-on 4.1 4.3 v dn lvd threshold in powerdown 3.5 3.8 v ol low level output voltage all output pins v dd = 5.0v; i ol = +10a v dd = 5.0v; i ol = + 3ma 0.1 0.8 v low level output voltage 30 ma sink i/o pins v dd = 5.0v; i ol = +10a v dd = 5.0v; i ol = +7ma v dd = 5.0v; i ol = +15ma 0.1 0.8 1.3 v oh high level output voltage all output pins v dd = 5.0v; i oh = -10a v dd = 5.0v; i oh = -3.0ma 4.9 3.5 v r pu pull-up resistance all input pins 40 100 350 ? reset pin 150 350 900 i il i ih input leakage current all input pins but reset v in = v ss (no pull-up configured) v in = v dd 0.1 1.0 a input leakage current reset pin v in = v ss v in = v dd -8 -16 -30 10 i dd supply current in reset mode v reset =v ss f osc =8mhz 7 ma supply current in run mode (2) v dd =5.0v f int =8mhz 7 ma supply current in wait mode (3) v dd =5.0v f int =8mhz 2.5 ma supply current in stop mode, with lvd disabled (3) i load =0ma v dd =5.0v 20 a supply current in stop mode, with lvd enabled (3) i load =0ma v dd =5.0v 500 retention eprom data retention t a = 55c 10 years
67/79 ST62T55CM-AUTO st62t65cm-auto dc electrical characteristics (cont?d) (t a = -40 to +85c unless otherwise specified)) note: (*) all peripherals in stand-by. 6.4 ac electrical characteristics (t a = -40 to +125c unless otherwise specified) notes: 1. period for which v dd has to be connected at 0v to allow internal reset function at next power-up. 2 an oscillator frequency above 1mhz is recommended for reliable a/d results. 3. measure performed with oscin pin soldered on pcb, with an around 2pf equivalent capacitance. symbol parameter test conditions value unit min. typ. max. v up lvd threshold in power-on v dn +50 mv 4.1 4.3 v v dn lvd threshold in powerdown 3.6 3.8 v up -50 mv v v ol low level output voltage all output pins v dd = 5.0v; i ol = +10a v dd = 5.0v; i ol = + 5ma v dd = 5.0v; i ol = + 10mav 0.1 0.8 1.2 v low level output voltage 30 ma sink i/o pins v dd = 5.0v; i ol = +10a v dd = 5.0v; i ol = +10ma v dd = 5.0v; i ol = +20ma v dd = 5.0v; i ol = +30ma 0.1 0.8 1.3 2.0 v oh high level output voltage all output pins v dd = 5.0v; i oh = -10a v dd = 5.0v; i oh = -5.0ma 4.9 3.5 v i dd supply current in stop mode, with lvd disabled (*) i load =0ma v dd =5.0v 10 a symbol parameter test conditions value unit min. ty p. max. t rec supply recovery time (1) 100 ms t wee eeprom write time t a = 25c t a = 85c t a = 125c 5 10 20 10 20 30 ms endurance (2) eeprom write/erase cycle q a l ot acceptance (25c) 300,000 1 million cycles retention eeprom data retention t a = 55c 10 years f lfao internal frequency with lfao active 200 400 800 khz f osg internal frequency with osg enabled 2) v dd = 3v v dd = 3.6v v dd = 4.5v v dd = 6v 1 1 2 2 f osc mhz f rc internal frequency with rc oscilla - tor and osg disabled 2) 3) vdd=5.0v (except 626xb rom) r=47k ? r=100k ? r=470k ? 4 2.7 800 5 3.2 850 5.8 3.5 900 mhz mhz khz vdd=5.0v (626xb rom) r=10k ? r=27k ? r=67k ? r=100k ? 6.3 4.7 2.8 2.2 8.2 5.9 3.6 2.8 9.8 7 4.3 3.4 mhz mhz mhz mhz c in input capacitance all inputs pins 10 pf c out output capacitance all outputs pins 10 pf
68/79 ST62T55CM-AUTO st62t65cm-auto 6.5 a/d converter characteristics (t a = -40 to +125c unless otherwise specified) notes : 1. noise at vdd, vss <10mv 2. with oscillator frequencies less than 1mhz, the a/d converter accuracy is decreased. 6.6 timer characteristics (t a = -40 to +125c unless otherwise specified) 6.7 spi characteristics (t a = -40 to +125c unless otherwise specified) 6.8 artimer electrical characteristics (t a = -40 to +125c unless otherwise specified) symbol parameter test conditions value unit min. typ. max. res resolution 8 bit a tot total accuracy (1) (2) f osc > 1.2mhz f osc > 32khz 2 4 lsb t c conversion time f osc = 8mhz (t a < 85c) f osc = 4 mhz 70 140 s zir zero input reading conversion result when v in = v ss 00 hex fsr full scale reading conversion result when v in = v dd ff hex ad i analog input current during conversion v dd = 4.5v 1.0 a ac in analog input capacitance 2 5 pf symbol parameter test conditions value unit min. typ. max. f in input frequency on timer pin mhz t w pulse width at timer pin v dd = 3.0v v dd > 4.5v 1 125 s ns f int 4 --------- - symbol parameter test conditions value unit min. typ. max. f cl clock frequency applied on scl 500 khz t su set-up time applied on sin 250 ns t h hold time applied onsin 50 ns symbol parameter test conditions value unit min typ max f in input frequency on artimin pin run and wait modes mhz stop mode 2
69/79 ST62T55CM-AUTO st62t65cm-auto figure 36. vol versus iol on all i/o port at vdd=5v figure 37. vol versus iol on all i/o port at t=25c figure 38. vol versus iol for high sink (30ma) i/oports at t=25c this curves represents typical variations and is given for guidance only this curves represents typical variations and is given for guidance only this curves represents typical variations and is given for guidance only
70/79 ST62T55CM-AUTO st62t65cm-auto figure 39. vol versus iol for high sink (30ma) i/o ports at vdd=5v figure 40. voh versus ioh on all i/o port at 25c figure 41. voh versus ioh on all i/o port at vdd=5v this curves represents typical variat ions and is given for guidance only this curves represents typical variations and is given for guidance only this curves represents typical variations and is given for guidance only
71/79 ST62T55CM-AUTO st62t65cm-auto figure 42. idd wait versus v dd at 8 mhz for otp devices figure 43. idd stop versus v dd for otp devices figure 44. idd stop versus v dd for rom devices this curves represents typical variations and is given for guidance only this curves represents typical variations and is given for guidance only this curves represents typical variations and is given for guidance only
72/79 ST62T55CM-AUTO st62t65cm-auto figure 45. idd wait versus v dd at 8mhz for rom devices figure 46. idd run versus v dd at 8 mhz for rom and otp devices figure 47. lvd thresholds versus temperature this curves represents typical variations and is given for guidance only this curves represents typical variat ions and is given for guidance only this curves represents typical variat ions and is given for guidance only
73/79 ST62T55CM-AUTO st62t65cm-auto figure 48. rc frequency versus v dd for rom st626xb only figure 49. rc frequency versus v dd (except for st626xb rom devices) this curves represents typical variations and is given for guidance only this curves represents typical variat ions and is given for guidance only
74/79 ST62T55CM-AUTO st62t65cm-auto 7 general information 7.1 package mechanical data figure 50. 28-pin plastic small outline package, 300-mil width figure 51. 28-ceramic dual in line package, 600-mil width dim. mm inches min typ max min typ max a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 17.70 18.10 0.697 0.713 e 7.40 7.60 0.291 0.299 e 1.27 0.050 h 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 0 8 0 8 l 0.40 1.27 0.016 0.050 number of pins n 28 h x 45 c l a a a1 e b d h e l dim. mm inches min typ max min typ max a 4.17 0.164 a1 0.76 0.030 b 0.36 0.46 0.56 0.014 0.018 0.022 b1 0.76 1.27 1.78 0.030 0.050 0.070 c 0.20 0.25 0.38 0.008 0.010 0.015 d 34.95 35.56 36.17 1.376 1.400 1.424 d1 33.02 1.300 e1 14.61 15.11 15.62 0.575 0.595 0.615 e 2.54 0.100 g 12.70 12.95 13.21 0.500 0.510 0.520 g1 12.70 12.95 13.21 0.500 0.510 0.520 g2 1.14 0.045 l 2.92 5.08 0.115 0.200 s 1.27 0.050 ? 8.89 0.350 number of pins n28 cdip28w
75/79 ST62T55CM-AUTO st62t65cm-auto 7.2 soldering information in accordance with the rohs european directive, all stmicroelectronics packages have been con - verted to lead-free technology, named eco- pack ? . ecopack ? packages are qualified according to the jedec std-020b compliant soldering profile. detailed information on the stmicroelectronics ecopack ? transition program is available on www.st.com/stonline/lead free/, with specific technical application notes covering the main technical aspects related to lead-free conversion (an2033, an2034, an2035, an2036). forward compatibility ecopack ? lqfp packages are fully compatible with lead (pb) containing soldering process (see application note an2034). table 24. soldering compatibility (wave and reflow soldering process) 7.3 otp/eprom version or dering information table 25. otp/eprom version ordering information notes: 1. please contact local sales office for ordering information 7.4 important note for otp devices, data retention an d programmability must be guaranteed by a screening procedure. re - fer to application note an886. package plating material devices pb solder paste pb-free solder paste so28 nipdau yes yes sales type programmemory (bytes) eeprom (bytes) temperature range package st62e65cf1 3884 (eprom) 128 0 to +70c cdip20 1) st62t55cma st62t55cmc 3884 (otp) none -40 to + 85c -40 to + 125c pso28 st62t65cma st62t65cmc 3884 (otp) 128 -40 to + 85c -40 to + 125c pso28
76/79 ST62T55CM-AUTO st62t65cm-auto 7.5 fastrom version general description the st62p55c and st62p65c are the f actory a dvanced s ervice t echnique rom (fastrom) versions of st62t55c and st62t65c otp devic - es. they offer the same functionality as otp devices, selecting as fastrom options the options de - fined in the programmable option byte of the otp version. 7.6 fastrom version ordering information the following section deals with the procedure for transfer of customer code s to stmicroelectronics. 7.6.1 transfer of customer code customer code is made up of the rom contents and the list of the selected fastrom options. the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file generated by the development tool. all unused bytes must be set to ffh. the selected options are communicated to stmi - croelectronics using the correctly filled option list appended. see page 77 . 7.6.2 listing generati on and verification when stmicroelectronics receives the user?s rom contents, a computer listing is generated from it. this listing refe rs exactly to the rom con - tents and options which will be used to produce the specified mcu. the lis ting is then returned to the customer who must thoroughly check, com - plete, sign and return it to stmicroelectronics. the signed listing forms a part of the contractual agree - ment for the production of the specific customer mcu. the stmicroelectronics sales organization will be pleased to provide detailed information on con - tractual points. table 26. rom memory map st62p55c/p65c table 27. fastrom version ordering information (*) advanced information device address description 0000h-007fh 0080h-0f9fh 0fa0h-0fefh 0ff0h-0ff7h 0ff8h-0ffbh 0ffch-0ffdh 0ffeh-0fffh reserved user rom reserved interrupt vectors reserved nmi interrupt vector reset vector sales type rom eeprom (bytes) temperature range package st62p55cma/xxx 3884 bytes none -40 to + 85c pso28 st62p55cmc/xxx (*) -40 to + 125c st62p65cma/xxx 128 -40 to + 85c st62p65cmc/xxx (*) -40 to + 125c
77/79 ST62T55CM-AUTO st62t65cm-auto st62p55cm/p65cm microcontroller option list customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . stmicroelectronics references: device: [ ] st62p55cm (4 kb) [ ] st62p65cm (4 kb) package: [ ] dual in line plastic [ ] small outline plastic with conditioning [ ] shrink small outline plastic with conditioning conditioning option: [ ] standard (tube) [ ] tape & reel temperature range: [ ] - 40c to + 85c [ ] - 40c to + 125c marking: [ ] standard marking [ ] special marking (rom only): pso28 (8 char. max): _ _ _ _ _ _ _ _ authorized characters are letters, di gits, '.', '-', '/' and spaces only. oscillator safeguard*: [ ] enabled [ ] disabled oscillator selecti on: [ ] quartz crystal / ceramic resonator [ ] rc network reset delay [ ] 32768 cycle delay [ ] 2048 cycle delay watchdog selection: [ ] software activation [ ] hardware activation pb1:pb0 pull-up at reset*: [ ] enabled [ ] disabled pb3:pb2 pull-up at reset*: [ ] enabled [ ] disabled external stop mode control: [ ] enabled [ ] disabled readout protection: [ ] enabled [ ] disabled low voltage detector*: [ ] enabled [ ] disabled nmi pull-up*: [ ] enabled [ ] disabled adc synchro*: [ ] enabled [ ] disabled comments: oscillator frequency in the applicat ion: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply operating range in the applic ation: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . date: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
78/79 ST62T55CM-AUTO st62t65cm-auto 8 summary of changes date revision main changes 13-nov-2007 1 document created from the st62t55c/st 62t65c/st62e65c, version 2.9, released july 2001. differences between version 2.9 and current automotive version 1 are as follows: automotive root part numbers, st62t55c m-auto and st62t65cm-auto created on page 1 fastrom information added to page 1 and fastrom cover page removed from page 77 updated ?device summary? on page 1 to include only automotive devices pdip28 and ss0p28 packages removed from page 1 , ?package mechanical da - ta? on page 74 , table 25, ?. otp/eprom version ordering information,? on page 75 , table 27, ?. fastrom version ordering information,? on page 76 and ?st62p55cm/p65cm microcontroller option list? on page 77 replaced 255 by 256 in the formula for max resolution artimout duty cycle in section 4.3.2 on page 45 altered note in ?capture mode with rese t of counter and prescaler, and pwm gener - ation? paragraph on page 48 added a note in the description of armc register in section 4.3.3 on page 49 added section 7.2 soldering information and section 7.4 important note on page 75 updated otp sales types and added footnote 1 to table 25 updated fastrom sales types in table 27 removed rom device section and removed references to rom device in the ?st62p55cm/p65cm microcontroller option list? on page 77 updated temperature ranges and package information in ?st62p55cm/p65cm mi - crocontroller option list? on page 77 section 7.3 ordering information changed to section 7.3 otp/eprom ver - sion ordering information removed section 8 general description section 8.1 introduction changed to section 7.5 fastrom version general description section 8.2 ordering information changed to section 7.6 fastrom version ordering information
79/79 ST62T55CM-AUTO st62t65cm-auto please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in mi litary, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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